#[doc = "Register `PWR_DFT_SELECT` reader"]
pub struct R(crate::R<PWR_DFT_SELECT_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PWR_DFT_SELECT_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PWR_DFT_SELECT_SPEC>> for R {
    fn from(reader: crate::R<PWR_DFT_SELECT_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PWR_DFT_SELECT` writer"]
pub struct W(crate::W<PWR_DFT_SELECT_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PWR_DFT_SELECT_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PWR_DFT_SELECT_SPEC>> for W {
    fn from(writer: crate::W<PWR_DFT_SELECT_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `TVMON1_SEL` reader - Select source for PWRSYS ADFT output #1:?0: not connected (default)?1: vnwell?2: vccq?3: vccd_sw?4: vcclfclk?5: vcchib?6: vccdpslp?7: vccqr"]
pub struct TVMON1_SEL_R(crate::FieldReader<u8, u8>);
impl TVMON1_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        TVMON1_SEL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for TVMON1_SEL_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `TVMON1_SEL` writer - Select source for PWRSYS ADFT output #1:?0: not connected (default)?1: vnwell?2: vccq?3: vccd_sw?4: vcclfclk?5: vcchib?6: vccdpslp?7: vccqr"]
pub struct TVMON1_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> TVMON1_SEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
        self.w
    }
}
#[doc = "Field `TVMON2_SEL` reader - Select source for PWRSYS ADFT output #2:?0: not connected (default)?1: not connected?2: Boot Reference biasn?3: Boot Reference nprot?4: DO NOT USE. Unsafely diode couples vccd_sw to bootref 800mV reference.?5: Boot Reference 800mv?6: not connected?7: not connected"]
pub struct TVMON2_SEL_R(crate::FieldReader<u8, u8>);
impl TVMON2_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        TVMON2_SEL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for TVMON2_SEL_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `TVMON2_SEL` writer - Select source for PWRSYS ADFT output #2:?0: not connected (default)?1: not connected?2: Boot Reference biasn?3: Boot Reference nprot?4: DO NOT USE. Unsafely diode couples vccd_sw to bootref 800mV reference.?5: Boot Reference 800mv?6: not connected?7: not connected"]
pub struct TVMON2_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> TVMON2_SEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
        self.w
    }
}
#[doc = "Field `BYPASS` reader - Forces regulator into bypass mode. Disables active mode regulator and allows most switches and other regulators to be manually controlled though other bits in this register.."]
pub struct BYPASS_R(crate::FieldReader<bool, bool>);
impl BYPASS_R {
    pub(crate) fn new(bits: bool) -> Self {
        BYPASS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BYPASS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BYPASS` writer - Forces regulator into bypass mode. Disables active mode regulator and allows most switches and other regulators to be manually controlled though other bits in this register.."]
pub struct BYPASS_W<'a> {
    w: &'a mut W,
}
impl<'a> BYPASS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
        self.w
    }
}
#[doc = "Field `ACTIVE_EN` reader - Force active regulator on. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct ACTIVE_EN_R(crate::FieldReader<bool, bool>);
impl ACTIVE_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        ACTIVE_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ACTIVE_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ACTIVE_EN` writer - Force active regulator on. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct ACTIVE_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> ACTIVE_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
        self.w
    }
}
#[doc = "Field `ACTIVE_INRUSH_DIS` reader - Force disable of active regulator inrush current limiter. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct ACTIVE_INRUSH_DIS_R(crate::FieldReader<bool, bool>);
impl ACTIVE_INRUSH_DIS_R {
    pub(crate) fn new(bits: bool) -> Self {
        ACTIVE_INRUSH_DIS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ACTIVE_INRUSH_DIS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ACTIVE_INRUSH_DIS` writer - Force disable of active regulator inrush current limiter. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct ACTIVE_INRUSH_DIS_W<'a> {
    w: &'a mut W,
}
impl<'a> ACTIVE_INRUSH_DIS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
        self.w
    }
}
#[doc = "Field `LPCOMP_DIS` reader - When set disables the LPCOMP. Only do this when the LPCOMP outputs are properly bypassed using the POWER_UP_* bits and also PWR_DFT_KEY.DFT_MODE=1. Only works when BYPASS=1. Intended for LPCOMP testing."]
pub struct LPCOMP_DIS_R(crate::FieldReader<bool, bool>);
impl LPCOMP_DIS_R {
    pub(crate) fn new(bits: bool) -> Self {
        LPCOMP_DIS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for LPCOMP_DIS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LPCOMP_DIS` writer - When set disables the LPCOMP. Only do this when the LPCOMP outputs are properly bypassed using the POWER_UP_* bits and also PWR_DFT_KEY.DFT_MODE=1. Only works when BYPASS=1. Intended for LPCOMP testing."]
pub struct LPCOMP_DIS_W<'a> {
    w: &'a mut W,
}
impl<'a> LPCOMP_DIS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
        self.w
    }
}
#[doc = "Field `BLEED_EN` reader - When set enables bleeder cells on various switched power nets to accelerate discharge during retention testing."]
pub struct BLEED_EN_R(crate::FieldReader<bool, bool>);
impl BLEED_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        BLEED_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BLEED_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BLEED_EN` writer - When set enables bleeder cells on various switched power nets to accelerate discharge during retention testing."]
pub struct BLEED_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> BLEED_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
        self.w
    }
}
#[doc = "Field `IPOR_EN` reader - Force IPOR_EN signal high. Only works when BYPASS=1. Intended for IPOR/HVPOR IDDQ testing. You must bypass the IO cells using PWR_DFT_KEY.IO_DISABLE_BYPASS and .KEY16 before setting this bit."]
pub struct IPOR_EN_R(crate::FieldReader<bool, bool>);
impl IPOR_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        IPOR_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for IPOR_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `IPOR_EN` writer - Force IPOR_EN signal high. Only works when BYPASS=1. Intended for IPOR/HVPOR IDDQ testing. You must bypass the IO cells using PWR_DFT_KEY.IO_DISABLE_BYPASS and .KEY16 before setting this bit."]
pub struct IPOR_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> IPOR_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
        self.w
    }
}
#[doc = "Field `POWER_UP_RAW_BYP` reader - When set, the LPCOMP output is controllable by POWER_UP_RAW_CTL. Only works when BYPASS=1. Intended for testing quiet regulator delayline, active regulator, and hibernate/deepsleep regulator."]
pub struct POWER_UP_RAW_BYP_R(crate::FieldReader<bool, bool>);
impl POWER_UP_RAW_BYP_R {
    pub(crate) fn new(bits: bool) -> Self {
        POWER_UP_RAW_BYP_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for POWER_UP_RAW_BYP_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `POWER_UP_RAW_BYP` writer - When set, the LPCOMP output is controllable by POWER_UP_RAW_CTL. Only works when BYPASS=1. Intended for testing quiet regulator delayline, active regulator, and hibernate/deepsleep regulator."]
pub struct POWER_UP_RAW_BYP_W<'a> {
    w: &'a mut W,
}
impl<'a> POWER_UP_RAW_BYP_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
        self.w
    }
}
#[doc = "Field `POWER_UP_RAW_CTL` reader - Value to force onto power_up_raw_hv. Only works when POWER_UP_RAW_BYP=1."]
pub struct POWER_UP_RAW_CTL_R(crate::FieldReader<bool, bool>);
impl POWER_UP_RAW_CTL_R {
    pub(crate) fn new(bits: bool) -> Self {
        POWER_UP_RAW_CTL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for POWER_UP_RAW_CTL_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `POWER_UP_RAW_CTL` writer - Value to force onto power_up_raw_hv. Only works when POWER_UP_RAW_BYP=1."]
pub struct POWER_UP_RAW_CTL_W<'a> {
    w: &'a mut W,
}
impl<'a> POWER_UP_RAW_CTL_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
        self.w
    }
}
#[doc = "Field `DEEPSLEEP_EN` reader - Force DeepSleep Regulator on. Only works when BYPASS=1. Intended for DeepSleep Regulator IDDQ testing."]
pub struct DEEPSLEEP_EN_R(crate::FieldReader<bool, bool>);
impl DEEPSLEEP_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        DEEPSLEEP_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DEEPSLEEP_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DEEPSLEEP_EN` writer - Force DeepSleep Regulator on. Only works when BYPASS=1. Intended for DeepSleep Regulator IDDQ testing."]
pub struct DEEPSLEEP_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> DEEPSLEEP_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
        self.w
    }
}
#[doc = "Field `RSVD_BYPASS` reader - Reserved, unused register. Only works when BYPASS=1."]
pub struct RSVD_BYPASS_R(crate::FieldReader<bool, bool>);
impl RSVD_BYPASS_R {
    pub(crate) fn new(bits: bool) -> Self {
        RSVD_BYPASS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for RSVD_BYPASS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RSVD_BYPASS` writer - Reserved, unused register. Only works when BYPASS=1."]
pub struct RSVD_BYPASS_W<'a> {
    w: &'a mut W,
}
impl<'a> RSVD_BYPASS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
        self.w
    }
}
#[doc = "Field `NWELL_OPEN` reader - Force switch between Vnwell and Vcchib open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct NWELL_OPEN_R(crate::FieldReader<bool, bool>);
impl NWELL_OPEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        NWELL_OPEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for NWELL_OPEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `NWELL_OPEN` writer - Force switch between Vnwell and Vcchib open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct NWELL_OPEN_W<'a> {
    w: &'a mut W,
}
impl<'a> NWELL_OPEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
        self.w
    }
}
#[doc = "Field `HIBERNATE_OPEN` reader - Force switch between Vcchib and Vccdpslp open. Only works when BYPASS=1, PWR_DFT_KEY.KEY16 is set to the key, and PWR_DFT_KEY.DFT_MODE=1. Intended for IDDQ testing."]
pub struct HIBERNATE_OPEN_R(crate::FieldReader<bool, bool>);
impl HIBERNATE_OPEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        HIBERNATE_OPEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HIBERNATE_OPEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIBERNATE_OPEN` writer - Force switch between Vcchib and Vccdpslp open. Only works when BYPASS=1, PWR_DFT_KEY.KEY16 is set to the key, and PWR_DFT_KEY.DFT_MODE=1. Intended for IDDQ testing."]
pub struct HIBERNATE_OPEN_W<'a> {
    w: &'a mut W,
}
impl<'a> HIBERNATE_OPEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
        self.w
    }
}
#[doc = "Field `DEEPSLEEP_OPEN` reader - Force switch between Vccdpslp and Vccd open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct DEEPSLEEP_OPEN_R(crate::FieldReader<bool, bool>);
impl DEEPSLEEP_OPEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        DEEPSLEEP_OPEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DEEPSLEEP_OPEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DEEPSLEEP_OPEN` writer - Force switch between Vccdpslp and Vccd open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct DEEPSLEEP_OPEN_W<'a> {
    w: &'a mut W,
}
impl<'a> DEEPSLEEP_OPEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
        self.w
    }
}
#[doc = "Field `QUIET_OPEN` reader - Force switch between Vccq and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct QUIET_OPEN_R(crate::FieldReader<bool, bool>);
impl QUIET_OPEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        QUIET_OPEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for QUIET_OPEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `QUIET_OPEN` writer - Force switch between Vccq and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct QUIET_OPEN_W<'a> {
    w: &'a mut W,
}
impl<'a> QUIET_OPEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
        self.w
    }
}
#[doc = "Field `LFCLK_OPEN` reader - Force switch between Vcclfclk and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct LFCLK_OPEN_R(crate::FieldReader<bool, bool>);
impl LFCLK_OPEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        LFCLK_OPEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for LFCLK_OPEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LFCLK_OPEN` writer - Force switch between Vcclfclk and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct LFCLK_OPEN_W<'a> {
    w: &'a mut W,
}
impl<'a> LFCLK_OPEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
        self.w
    }
}
#[doc = "Field `QUIET_EN` reader - Force Vccq regulator on/off. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct QUIET_EN_R(crate::FieldReader<bool, bool>);
impl QUIET_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        QUIET_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for QUIET_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `QUIET_EN` writer - Force Vccq regulator on/off. Only works when BYPASS=1. Intended for IDDQ testing."]
pub struct QUIET_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> QUIET_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
        self.w
    }
}
#[doc = "Field `BREF_EN` reader - Enables the boot reference currents. Do not clear this bit unless he active regulator, quiet regulator, or LPCOMP are bypassed. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_EN_R(crate::FieldReader<bool, bool>);
impl BREF_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        BREF_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BREF_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BREF_EN` writer - Enables the boot reference currents. Do not clear this bit unless he active regulator, quiet regulator, or LPCOMP are bypassed. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> BREF_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
        self.w
    }
}
#[doc = "Field `BREF_OUTEN` reader - Enables the output stage of the LDO reference selector. Do not clear this bit when the active regulator is operating. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_OUTEN_R(crate::FieldReader<bool, bool>);
impl BREF_OUTEN_R {
    pub(crate) fn new(bits: bool) -> Self {
        BREF_OUTEN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BREF_OUTEN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BREF_OUTEN` writer - Enables the output stage of the LDO reference selector. Do not clear this bit when the active regulator is operating. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_OUTEN_W<'a> {
    w: &'a mut W,
}
impl<'a> BREF_OUTEN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
        self.w
    }
}
#[doc = "Field `BREF_REFSW` reader - Controls the power system reference source?0: boot reference?1: Low voltage bandgap (LVBG)?Using the LVBG reference improves PSRR. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_REFSW_R(crate::FieldReader<bool, bool>);
impl BREF_REFSW_R {
    pub(crate) fn new(bits: bool) -> Self {
        BREF_REFSW_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BREF_REFSW_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BREF_REFSW` writer - Controls the power system reference source?0: boot reference?1: Low voltage bandgap (LVBG)?Using the LVBG reference improves PSRR. Only works when BYPASS=1. Intended for characterization and testing."]
pub struct BREF_REFSW_W<'a> {
    w: &'a mut W,
}
impl<'a> BREF_REFSW_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
        self.w
    }
}
#[doc = "Field `BREF_TESTMODE` reader - Puts the bootref in testmode. Intended for characterization and testing."]
pub struct BREF_TESTMODE_R(crate::FieldReader<bool, bool>);
impl BREF_TESTMODE_R {
    pub(crate) fn new(bits: bool) -> Self {
        BREF_TESTMODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for BREF_TESTMODE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BREF_TESTMODE` writer - Puts the bootref in testmode. Intended for characterization and testing."]
pub struct BREF_TESTMODE_W<'a> {
    w: &'a mut W,
}
impl<'a> BREF_TESTMODE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
        self.w
    }
}
#[doc = "Field `NWELL_DIS` reader - Controls the vnwell level during deep sleep and hibernate. When set, the nwell regulator is disabled. When this bit is set, the Vnwell rail will be shorted to Vcchib rail (nwell_short)."]
pub struct NWELL_DIS_R(crate::FieldReader<bool, bool>);
impl NWELL_DIS_R {
    pub(crate) fn new(bits: bool) -> Self {
        NWELL_DIS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for NWELL_DIS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `NWELL_DIS` writer - Controls the vnwell level during deep sleep and hibernate. When set, the nwell regulator is disabled. When this bit is set, the Vnwell rail will be shorted to Vcchib rail (nwell_short)."]
pub struct NWELL_DIS_W<'a> {
    w: &'a mut W,
}
impl<'a> NWELL_DIS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
        self.w
    }
}
#[doc = "Field `HVMON_DFT_OVR` reader - Overrides the trim values coming from NVLatches to the values stored in the HV Monitor. Allows char & test of the NVLatches without disturbing trims."]
pub struct HVMON_DFT_OVR_R(crate::FieldReader<bool, bool>);
impl HVMON_DFT_OVR_R {
    pub(crate) fn new(bits: bool) -> Self {
        HVMON_DFT_OVR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HVMON_DFT_OVR_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HVMON_DFT_OVR` writer - Overrides the trim values coming from NVLatches to the values stored in the HV Monitor. Allows char & test of the NVLatches without disturbing trims."]
pub struct HVMON_DFT_OVR_W<'a> {
    w: &'a mut W,
}
impl<'a> HVMON_DFT_OVR_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
        self.w
    }
}
#[doc = "Field `IMO_REFGEN_DIS` reader - Disables the IMO reference generator to allow testing the current references. A side-effect of setting this bit is that the SRSS outputs vbias_ptat and vbias_casc_ptat are shorted to vccq."]
pub struct IMO_REFGEN_DIS_R(crate::FieldReader<bool, bool>);
impl IMO_REFGEN_DIS_R {
    pub(crate) fn new(bits: bool) -> Self {
        IMO_REFGEN_DIS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for IMO_REFGEN_DIS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `IMO_REFGEN_DIS` writer - Disables the IMO reference generator to allow testing the current references. A side-effect of setting this bit is that the SRSS outputs vbias_ptat and vbias_casc_ptat are shorted to vccq."]
pub struct IMO_REFGEN_DIS_W<'a> {
    w: &'a mut W,
}
impl<'a> IMO_REFGEN_DIS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
        self.w
    }
}
#[doc = "Field `POWER_UP_ACTIVE` reader - When set, forces pwrgood=1 for active regulator. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
pub struct POWER_UP_ACTIVE_R(crate::FieldReader<bool, bool>);
impl POWER_UP_ACTIVE_R {
    pub(crate) fn new(bits: bool) -> Self {
        POWER_UP_ACTIVE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for POWER_UP_ACTIVE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `POWER_UP_ACTIVE` writer - When set, forces pwrgood=1 for active regulator. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
pub struct POWER_UP_ACTIVE_W<'a> {
    w: &'a mut W,
}
impl<'a> POWER_UP_ACTIVE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
        self.w
    }
}
#[doc = "Field `POWER_UP_HIBDPSLP` reader - When set, forces pwrg_actdig=1 for hibernate/deepsleep circuits. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
pub struct POWER_UP_HIBDPSLP_R(crate::FieldReader<bool, bool>);
impl POWER_UP_HIBDPSLP_R {
    pub(crate) fn new(bits: bool) -> Self {
        POWER_UP_HIBDPSLP_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for POWER_UP_HIBDPSLP_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `POWER_UP_HIBDPSLP` writer - When set, forces pwrg_actdig=1 for hibernate/deepsleep circuits. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
pub struct POWER_UP_HIBDPSLP_W<'a> {
    w: &'a mut W,
}
impl<'a> POWER_UP_HIBDPSLP_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:2 - Select source for PWRSYS ADFT output #1:?0: not connected (default)?1: vnwell?2: vccq?3: vccd_sw?4: vcclfclk?5: vcchib?6: vccdpslp?7: vccqr"]
    #[inline(always)]
    pub fn tvmon1_sel(&self) -> TVMON1_SEL_R {
        TVMON1_SEL_R::new((self.bits & 0x07) as u8)
    }
    #[doc = "Bits 3:5 - Select source for PWRSYS ADFT output #2:?0: not connected (default)?1: not connected?2: Boot Reference biasn?3: Boot Reference nprot?4: DO NOT USE. Unsafely diode couples vccd_sw to bootref 800mV reference.?5: Boot Reference 800mv?6: not connected?7: not connected"]
    #[inline(always)]
    pub fn tvmon2_sel(&self) -> TVMON2_SEL_R {
        TVMON2_SEL_R::new(((self.bits >> 3) & 0x07) as u8)
    }
    #[doc = "Bit 6 - Forces regulator into bypass mode. Disables active mode regulator and allows most switches and other regulators to be manually controlled though other bits in this register.."]
    #[inline(always)]
    pub fn bypass(&self) -> BYPASS_R {
        BYPASS_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - Force active regulator on. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn active_en(&self) -> ACTIVE_EN_R {
        ACTIVE_EN_R::new(((self.bits >> 7) & 0x01) != 0)
    }
    #[doc = "Bit 8 - Force disable of active regulator inrush current limiter. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn active_inrush_dis(&self) -> ACTIVE_INRUSH_DIS_R {
        ACTIVE_INRUSH_DIS_R::new(((self.bits >> 8) & 0x01) != 0)
    }
    #[doc = "Bit 9 - When set disables the LPCOMP. Only do this when the LPCOMP outputs are properly bypassed using the POWER_UP_* bits and also PWR_DFT_KEY.DFT_MODE=1. Only works when BYPASS=1. Intended for LPCOMP testing."]
    #[inline(always)]
    pub fn lpcomp_dis(&self) -> LPCOMP_DIS_R {
        LPCOMP_DIS_R::new(((self.bits >> 9) & 0x01) != 0)
    }
    #[doc = "Bit 10 - When set enables bleeder cells on various switched power nets to accelerate discharge during retention testing."]
    #[inline(always)]
    pub fn bleed_en(&self) -> BLEED_EN_R {
        BLEED_EN_R::new(((self.bits >> 10) & 0x01) != 0)
    }
    #[doc = "Bit 11 - Force IPOR_EN signal high. Only works when BYPASS=1. Intended for IPOR/HVPOR IDDQ testing. You must bypass the IO cells using PWR_DFT_KEY.IO_DISABLE_BYPASS and .KEY16 before setting this bit."]
    #[inline(always)]
    pub fn ipor_en(&self) -> IPOR_EN_R {
        IPOR_EN_R::new(((self.bits >> 11) & 0x01) != 0)
    }
    #[doc = "Bit 12 - When set, the LPCOMP output is controllable by POWER_UP_RAW_CTL. Only works when BYPASS=1. Intended for testing quiet regulator delayline, active regulator, and hibernate/deepsleep regulator."]
    #[inline(always)]
    pub fn power_up_raw_byp(&self) -> POWER_UP_RAW_BYP_R {
        POWER_UP_RAW_BYP_R::new(((self.bits >> 12) & 0x01) != 0)
    }
    #[doc = "Bit 13 - Value to force onto power_up_raw_hv. Only works when POWER_UP_RAW_BYP=1."]
    #[inline(always)]
    pub fn power_up_raw_ctl(&self) -> POWER_UP_RAW_CTL_R {
        POWER_UP_RAW_CTL_R::new(((self.bits >> 13) & 0x01) != 0)
    }
    #[doc = "Bit 14 - Force DeepSleep Regulator on. Only works when BYPASS=1. Intended for DeepSleep Regulator IDDQ testing."]
    #[inline(always)]
    pub fn deepsleep_en(&self) -> DEEPSLEEP_EN_R {
        DEEPSLEEP_EN_R::new(((self.bits >> 14) & 0x01) != 0)
    }
    #[doc = "Bit 15 - Reserved, unused register. Only works when BYPASS=1."]
    #[inline(always)]
    pub fn rsvd_bypass(&self) -> RSVD_BYPASS_R {
        RSVD_BYPASS_R::new(((self.bits >> 15) & 0x01) != 0)
    }
    #[doc = "Bit 16 - Force switch between Vnwell and Vcchib open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn nwell_open(&self) -> NWELL_OPEN_R {
        NWELL_OPEN_R::new(((self.bits >> 16) & 0x01) != 0)
    }
    #[doc = "Bit 17 - Force switch between Vcchib and Vccdpslp open. Only works when BYPASS=1, PWR_DFT_KEY.KEY16 is set to the key, and PWR_DFT_KEY.DFT_MODE=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn hibernate_open(&self) -> HIBERNATE_OPEN_R {
        HIBERNATE_OPEN_R::new(((self.bits >> 17) & 0x01) != 0)
    }
    #[doc = "Bit 18 - Force switch between Vccdpslp and Vccd open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn deepsleep_open(&self) -> DEEPSLEEP_OPEN_R {
        DEEPSLEEP_OPEN_R::new(((self.bits >> 18) & 0x01) != 0)
    }
    #[doc = "Bit 19 - Force switch between Vccq and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn quiet_open(&self) -> QUIET_OPEN_R {
        QUIET_OPEN_R::new(((self.bits >> 19) & 0x01) != 0)
    }
    #[doc = "Bit 20 - Force switch between Vcclfclk and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn lfclk_open(&self) -> LFCLK_OPEN_R {
        LFCLK_OPEN_R::new(((self.bits >> 20) & 0x01) != 0)
    }
    #[doc = "Bit 22 - Force Vccq regulator on/off. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn quiet_en(&self) -> QUIET_EN_R {
        QUIET_EN_R::new(((self.bits >> 22) & 0x01) != 0)
    }
    #[doc = "Bit 23 - Enables the boot reference currents. Do not clear this bit unless he active regulator, quiet regulator, or LPCOMP are bypassed. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_en(&self) -> BREF_EN_R {
        BREF_EN_R::new(((self.bits >> 23) & 0x01) != 0)
    }
    #[doc = "Bit 24 - Enables the output stage of the LDO reference selector. Do not clear this bit when the active regulator is operating. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_outen(&self) -> BREF_OUTEN_R {
        BREF_OUTEN_R::new(((self.bits >> 24) & 0x01) != 0)
    }
    #[doc = "Bit 25 - Controls the power system reference source?0: boot reference?1: Low voltage bandgap (LVBG)?Using the LVBG reference improves PSRR. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_refsw(&self) -> BREF_REFSW_R {
        BREF_REFSW_R::new(((self.bits >> 25) & 0x01) != 0)
    }
    #[doc = "Bit 26 - Puts the bootref in testmode. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_testmode(&self) -> BREF_TESTMODE_R {
        BREF_TESTMODE_R::new(((self.bits >> 26) & 0x01) != 0)
    }
    #[doc = "Bit 27 - Controls the vnwell level during deep sleep and hibernate. When set, the nwell regulator is disabled. When this bit is set, the Vnwell rail will be shorted to Vcchib rail (nwell_short)."]
    #[inline(always)]
    pub fn nwell_dis(&self) -> NWELL_DIS_R {
        NWELL_DIS_R::new(((self.bits >> 27) & 0x01) != 0)
    }
    #[doc = "Bit 28 - Overrides the trim values coming from NVLatches to the values stored in the HV Monitor. Allows char & test of the NVLatches without disturbing trims."]
    #[inline(always)]
    pub fn hvmon_dft_ovr(&self) -> HVMON_DFT_OVR_R {
        HVMON_DFT_OVR_R::new(((self.bits >> 28) & 0x01) != 0)
    }
    #[doc = "Bit 29 - Disables the IMO reference generator to allow testing the current references. A side-effect of setting this bit is that the SRSS outputs vbias_ptat and vbias_casc_ptat are shorted to vccq."]
    #[inline(always)]
    pub fn imo_refgen_dis(&self) -> IMO_REFGEN_DIS_R {
        IMO_REFGEN_DIS_R::new(((self.bits >> 29) & 0x01) != 0)
    }
    #[doc = "Bit 30 - When set, forces pwrgood=1 for active regulator. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
    #[inline(always)]
    pub fn power_up_active(&self) -> POWER_UP_ACTIVE_R {
        POWER_UP_ACTIVE_R::new(((self.bits >> 30) & 0x01) != 0)
    }
    #[doc = "Bit 31 - When set, forces pwrg_actdig=1 for hibernate/deepsleep circuits. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
    #[inline(always)]
    pub fn power_up_hibdpslp(&self) -> POWER_UP_HIBDPSLP_R {
        POWER_UP_HIBDPSLP_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:2 - Select source for PWRSYS ADFT output #1:?0: not connected (default)?1: vnwell?2: vccq?3: vccd_sw?4: vcclfclk?5: vcchib?6: vccdpslp?7: vccqr"]
    #[inline(always)]
    pub fn tvmon1_sel(&mut self) -> TVMON1_SEL_W {
        TVMON1_SEL_W { w: self }
    }
    #[doc = "Bits 3:5 - Select source for PWRSYS ADFT output #2:?0: not connected (default)?1: not connected?2: Boot Reference biasn?3: Boot Reference nprot?4: DO NOT USE. Unsafely diode couples vccd_sw to bootref 800mV reference.?5: Boot Reference 800mv?6: not connected?7: not connected"]
    #[inline(always)]
    pub fn tvmon2_sel(&mut self) -> TVMON2_SEL_W {
        TVMON2_SEL_W { w: self }
    }
    #[doc = "Bit 6 - Forces regulator into bypass mode. Disables active mode regulator and allows most switches and other regulators to be manually controlled though other bits in this register.."]
    #[inline(always)]
    pub fn bypass(&mut self) -> BYPASS_W {
        BYPASS_W { w: self }
    }
    #[doc = "Bit 7 - Force active regulator on. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn active_en(&mut self) -> ACTIVE_EN_W {
        ACTIVE_EN_W { w: self }
    }
    #[doc = "Bit 8 - Force disable of active regulator inrush current limiter. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn active_inrush_dis(&mut self) -> ACTIVE_INRUSH_DIS_W {
        ACTIVE_INRUSH_DIS_W { w: self }
    }
    #[doc = "Bit 9 - When set disables the LPCOMP. Only do this when the LPCOMP outputs are properly bypassed using the POWER_UP_* bits and also PWR_DFT_KEY.DFT_MODE=1. Only works when BYPASS=1. Intended for LPCOMP testing."]
    #[inline(always)]
    pub fn lpcomp_dis(&mut self) -> LPCOMP_DIS_W {
        LPCOMP_DIS_W { w: self }
    }
    #[doc = "Bit 10 - When set enables bleeder cells on various switched power nets to accelerate discharge during retention testing."]
    #[inline(always)]
    pub fn bleed_en(&mut self) -> BLEED_EN_W {
        BLEED_EN_W { w: self }
    }
    #[doc = "Bit 11 - Force IPOR_EN signal high. Only works when BYPASS=1. Intended for IPOR/HVPOR IDDQ testing. You must bypass the IO cells using PWR_DFT_KEY.IO_DISABLE_BYPASS and .KEY16 before setting this bit."]
    #[inline(always)]
    pub fn ipor_en(&mut self) -> IPOR_EN_W {
        IPOR_EN_W { w: self }
    }
    #[doc = "Bit 12 - When set, the LPCOMP output is controllable by POWER_UP_RAW_CTL. Only works when BYPASS=1. Intended for testing quiet regulator delayline, active regulator, and hibernate/deepsleep regulator."]
    #[inline(always)]
    pub fn power_up_raw_byp(&mut self) -> POWER_UP_RAW_BYP_W {
        POWER_UP_RAW_BYP_W { w: self }
    }
    #[doc = "Bit 13 - Value to force onto power_up_raw_hv. Only works when POWER_UP_RAW_BYP=1."]
    #[inline(always)]
    pub fn power_up_raw_ctl(&mut self) -> POWER_UP_RAW_CTL_W {
        POWER_UP_RAW_CTL_W { w: self }
    }
    #[doc = "Bit 14 - Force DeepSleep Regulator on. Only works when BYPASS=1. Intended for DeepSleep Regulator IDDQ testing."]
    #[inline(always)]
    pub fn deepsleep_en(&mut self) -> DEEPSLEEP_EN_W {
        DEEPSLEEP_EN_W { w: self }
    }
    #[doc = "Bit 15 - Reserved, unused register. Only works when BYPASS=1."]
    #[inline(always)]
    pub fn rsvd_bypass(&mut self) -> RSVD_BYPASS_W {
        RSVD_BYPASS_W { w: self }
    }
    #[doc = "Bit 16 - Force switch between Vnwell and Vcchib open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn nwell_open(&mut self) -> NWELL_OPEN_W {
        NWELL_OPEN_W { w: self }
    }
    #[doc = "Bit 17 - Force switch between Vcchib and Vccdpslp open. Only works when BYPASS=1, PWR_DFT_KEY.KEY16 is set to the key, and PWR_DFT_KEY.DFT_MODE=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn hibernate_open(&mut self) -> HIBERNATE_OPEN_W {
        HIBERNATE_OPEN_W { w: self }
    }
    #[doc = "Bit 18 - Force switch between Vccdpslp and Vccd open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn deepsleep_open(&mut self) -> DEEPSLEEP_OPEN_W {
        DEEPSLEEP_OPEN_W { w: self }
    }
    #[doc = "Bit 19 - Force switch between Vccq and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn quiet_open(&mut self) -> QUIET_OPEN_W {
        QUIET_OPEN_W { w: self }
    }
    #[doc = "Bit 20 - Force switch between Vcclfclk and Vccdpslp open. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn lfclk_open(&mut self) -> LFCLK_OPEN_W {
        LFCLK_OPEN_W { w: self }
    }
    #[doc = "Bit 22 - Force Vccq regulator on/off. Only works when BYPASS=1. Intended for IDDQ testing."]
    #[inline(always)]
    pub fn quiet_en(&mut self) -> QUIET_EN_W {
        QUIET_EN_W { w: self }
    }
    #[doc = "Bit 23 - Enables the boot reference currents. Do not clear this bit unless he active regulator, quiet regulator, or LPCOMP are bypassed. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_en(&mut self) -> BREF_EN_W {
        BREF_EN_W { w: self }
    }
    #[doc = "Bit 24 - Enables the output stage of the LDO reference selector. Do not clear this bit when the active regulator is operating. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_outen(&mut self) -> BREF_OUTEN_W {
        BREF_OUTEN_W { w: self }
    }
    #[doc = "Bit 25 - Controls the power system reference source?0: boot reference?1: Low voltage bandgap (LVBG)?Using the LVBG reference improves PSRR. Only works when BYPASS=1. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_refsw(&mut self) -> BREF_REFSW_W {
        BREF_REFSW_W { w: self }
    }
    #[doc = "Bit 26 - Puts the bootref in testmode. Intended for characterization and testing."]
    #[inline(always)]
    pub fn bref_testmode(&mut self) -> BREF_TESTMODE_W {
        BREF_TESTMODE_W { w: self }
    }
    #[doc = "Bit 27 - Controls the vnwell level during deep sleep and hibernate. When set, the nwell regulator is disabled. When this bit is set, the Vnwell rail will be shorted to Vcchib rail (nwell_short)."]
    #[inline(always)]
    pub fn nwell_dis(&mut self) -> NWELL_DIS_W {
        NWELL_DIS_W { w: self }
    }
    #[doc = "Bit 28 - Overrides the trim values coming from NVLatches to the values stored in the HV Monitor. Allows char & test of the NVLatches without disturbing trims."]
    #[inline(always)]
    pub fn hvmon_dft_ovr(&mut self) -> HVMON_DFT_OVR_W {
        HVMON_DFT_OVR_W { w: self }
    }
    #[doc = "Bit 29 - Disables the IMO reference generator to allow testing the current references. A side-effect of setting this bit is that the SRSS outputs vbias_ptat and vbias_casc_ptat are shorted to vccq."]
    #[inline(always)]
    pub fn imo_refgen_dis(&mut self) -> IMO_REFGEN_DIS_W {
        IMO_REFGEN_DIS_W { w: self }
    }
    #[doc = "Bit 30 - When set, forces pwrgood=1 for active regulator. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
    #[inline(always)]
    pub fn power_up_active(&mut self) -> POWER_UP_ACTIVE_W {
        POWER_UP_ACTIVE_W { w: self }
    }
    #[doc = "Bit 31 - When set, forces pwrg_actdig=1 for hibernate/deepsleep circuits. Combined with POWER_UP_RAW_CTL=0, this gives full control on this input for characterization and testing."]
    #[inline(always)]
    pub fn power_up_hibdpslp(&mut self) -> POWER_UP_HIBDPSLP_W {
        POWER_UP_HIBDPSLP_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Power DFT Mode Selection Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwr_dft_select](index.html) module"]
pub struct PWR_DFT_SELECT_SPEC;
impl crate::RegisterSpec for PWR_DFT_SELECT_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pwr_dft_select::R](R) reader structure"]
impl crate::Readable for PWR_DFT_SELECT_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pwr_dft_select::W](W) writer structure"]
impl crate::Writable for PWR_DFT_SELECT_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PWR_DFT_SELECT to value 0"]
impl crate::Resettable for PWR_DFT_SELECT_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
