#[doc = "Register `INTR_CAUSE` reader"]
pub struct R(crate::R<INTR_CAUSE_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<INTR_CAUSE_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<INTR_CAUSE_SPEC>> for R {
    fn from(reader: crate::R<INTR_CAUSE_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `INTR_CAUSE` writer"]
pub struct W(crate::W<INTR_CAUSE_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<INTR_CAUSE_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<INTR_CAUSE_SPEC>> for W {
    fn from(writer: crate::W<INTR_CAUSE_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PORT_INT` reader - Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects \"gpio_interrupts\\[i\\]\" for IO port i). The register is used when the system uses a shared/combined interrupt line \"gpio_interrupt\". The SW ISR reads the register to deternine which IO port(s) is responsible for the shared/combined interrupt line \"gpio_interrupt\". Once, the IO port(s) is determined, the IO port's INTR register is read to determine the IO pad(s) in the IO port that caused the interrupt."]
pub struct PORT_INT_R(crate::FieldReader<u16, u16>);
impl PORT_INT_R {
    pub(crate) fn new(bits: u16) -> Self {
        PORT_INT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PORT_INT_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl R {
    #[doc = "Bits 0:13 - Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects \"gpio_interrupts\\[i\\]\" for IO port i). The register is used when the system uses a shared/combined interrupt line \"gpio_interrupt\". The SW ISR reads the register to deternine which IO port(s) is responsible for the shared/combined interrupt line \"gpio_interrupt\". Once, the IO port(s) is determined, the IO port's INTR register is read to determine the IO pad(s) in the IO port that caused the interrupt."]
    #[inline(always)]
    pub fn port_int(&self) -> PORT_INT_R {
        PORT_INT_R::new((self.bits & 0x3fff) as u16)
    }
}
impl W {
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Interrupt port cause register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_cause](index.html) module"]
pub struct INTR_CAUSE_SPEC;
impl crate::RegisterSpec for INTR_CAUSE_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [intr_cause::R](R) reader structure"]
impl crate::Readable for INTR_CAUSE_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [intr_cause::W](W) writer structure"]
impl crate::Writable for INTR_CAUSE_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets INTR_CAUSE to value 0"]
impl crate::Resettable for INTR_CAUSE_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
