#[doc = "Register `PWR_PWRSYS_TRIM4` reader"]
pub struct R(crate::R<PWR_PWRSYS_TRIM4_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PWR_PWRSYS_TRIM4_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PWR_PWRSYS_TRIM4_SPEC>> for R {
    fn from(reader: crate::R<PWR_PWRSYS_TRIM4_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PWR_PWRSYS_TRIM4` writer"]
pub struct W(crate::W<PWR_PWRSYS_TRIM4_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PWR_PWRSYS_TRIM4_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PWR_PWRSYS_TRIM4_SPEC>> for W {
    fn from(writer: crate::W<PWR_PWRSYS_TRIM4_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `HIB_TRIM_NWELL` reader - Vnwell Leakage control?00= smart nwell regulation?01= regulate nwell to constant voltage. ?10= regulate nwell to vcchib + nfet diode?11= regulate nwell to vcchib + nfet diode"]
pub struct HIB_TRIM_NWELL_R(crate::FieldReader<u8, u8>);
impl HIB_TRIM_NWELL_R {
    pub(crate) fn new(bits: u8) -> Self {
        HIB_TRIM_NWELL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HIB_TRIM_NWELL_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIB_TRIM_NWELL` writer - Vnwell Leakage control?00= smart nwell regulation?01= regulate nwell to constant voltage. ?10= regulate nwell to vcchib + nfet diode?11= regulate nwell to vcchib + nfet diode"]
pub struct HIB_TRIM_NWELL_W<'a> {
    w: &'a mut W,
}
impl<'a> HIB_TRIM_NWELL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
        self.w
    }
}
#[doc = "Field `HIB_TRIM_LEAKAGE` reader - Enable Vcchib pass gate leakage control"]
pub struct HIB_TRIM_LEAKAGE_R(crate::FieldReader<bool, bool>);
impl HIB_TRIM_LEAKAGE_R {
    pub(crate) fn new(bits: bool) -> Self {
        HIB_TRIM_LEAKAGE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HIB_TRIM_LEAKAGE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIB_TRIM_LEAKAGE` writer - Enable Vcchib pass gate leakage control"]
pub struct HIB_TRIM_LEAKAGE_W<'a> {
    w: &'a mut W,
}
impl<'a> HIB_TRIM_LEAKAGE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
        self.w
    }
}
#[doc = "Field `HIB_TRIM_VOLTAGE` reader - Elevate output voltage?1= regulator hibernate 200mV higher ?0= nominal 1.4-1.6V range"]
pub struct HIB_TRIM_VOLTAGE_R(crate::FieldReader<bool, bool>);
impl HIB_TRIM_VOLTAGE_R {
    pub(crate) fn new(bits: bool) -> Self {
        HIB_TRIM_VOLTAGE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HIB_TRIM_VOLTAGE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIB_TRIM_VOLTAGE` writer - Elevate output voltage?1= regulator hibernate 200mV higher ?0= nominal 1.4-1.6V range"]
pub struct HIB_TRIM_VOLTAGE_W<'a> {
    w: &'a mut W,
}
impl<'a> HIB_TRIM_VOLTAGE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
        self.w
    }
}
#[doc = "Field `HIB_TRIM_REFERENCE` reader - Hibernate Reference trim?10=Trim reference by -27mV?01=Trim reference by +27mV?00= no trim"]
pub struct HIB_TRIM_REFERENCE_R(crate::FieldReader<u8, u8>);
impl HIB_TRIM_REFERENCE_R {
    pub(crate) fn new(bits: u8) -> Self {
        HIB_TRIM_REFERENCE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HIB_TRIM_REFERENCE_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIB_TRIM_REFERENCE` writer - Hibernate Reference trim?10=Trim reference by -27mV?01=Trim reference by +27mV?00= no trim"]
pub struct HIB_TRIM_REFERENCE_W<'a> {
    w: &'a mut W,
}
impl<'a> HIB_TRIM_REFERENCE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - Vnwell Leakage control?00= smart nwell regulation?01= regulate nwell to constant voltage. ?10= regulate nwell to vcchib + nfet diode?11= regulate nwell to vcchib + nfet diode"]
    #[inline(always)]
    pub fn hib_trim_nwell(&self) -> HIB_TRIM_NWELL_R {
        HIB_TRIM_NWELL_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bit 2 - Enable Vcchib pass gate leakage control"]
    #[inline(always)]
    pub fn hib_trim_leakage(&self) -> HIB_TRIM_LEAKAGE_R {
        HIB_TRIM_LEAKAGE_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - Elevate output voltage?1= regulator hibernate 200mV higher ?0= nominal 1.4-1.6V range"]
    #[inline(always)]
    pub fn hib_trim_voltage(&self) -> HIB_TRIM_VOLTAGE_R {
        HIB_TRIM_VOLTAGE_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bits 4:5 - Hibernate Reference trim?10=Trim reference by -27mV?01=Trim reference by +27mV?00= no trim"]
    #[inline(always)]
    pub fn hib_trim_reference(&self) -> HIB_TRIM_REFERENCE_R {
        HIB_TRIM_REFERENCE_R::new(((self.bits >> 4) & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bits 0:1 - Vnwell Leakage control?00= smart nwell regulation?01= regulate nwell to constant voltage. ?10= regulate nwell to vcchib + nfet diode?11= regulate nwell to vcchib + nfet diode"]
    #[inline(always)]
    pub fn hib_trim_nwell(&mut self) -> HIB_TRIM_NWELL_W {
        HIB_TRIM_NWELL_W { w: self }
    }
    #[doc = "Bit 2 - Enable Vcchib pass gate leakage control"]
    #[inline(always)]
    pub fn hib_trim_leakage(&mut self) -> HIB_TRIM_LEAKAGE_W {
        HIB_TRIM_LEAKAGE_W { w: self }
    }
    #[doc = "Bit 3 - Elevate output voltage?1= regulator hibernate 200mV higher ?0= nominal 1.4-1.6V range"]
    #[inline(always)]
    pub fn hib_trim_voltage(&mut self) -> HIB_TRIM_VOLTAGE_W {
        HIB_TRIM_VOLTAGE_W { w: self }
    }
    #[doc = "Bits 4:5 - Hibernate Reference trim?10=Trim reference by -27mV?01=Trim reference by +27mV?00= no trim"]
    #[inline(always)]
    pub fn hib_trim_reference(&mut self) -> HIB_TRIM_REFERENCE_W {
        HIB_TRIM_REFERENCE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Power System Trim Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwr_pwrsys_trim4](index.html) module"]
pub struct PWR_PWRSYS_TRIM4_SPEC;
impl crate::RegisterSpec for PWR_PWRSYS_TRIM4_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pwr_pwrsys_trim4::R](R) reader structure"]
impl crate::Readable for PWR_PWRSYS_TRIM4_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pwr_pwrsys_trim4::W](W) writer structure"]
impl crate::Writable for PWR_PWRSYS_TRIM4_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PWR_PWRSYS_TRIM4 to value 0"]
impl crate::Resettable for PWR_PWRSYS_TRIM4_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
