#[doc = "Register `SAMPLE_CTRL` reader"]
pub struct R(crate::R<SAMPLE_CTRL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<SAMPLE_CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<SAMPLE_CTRL_SPEC>> for R {
    fn from(reader: crate::R<SAMPLE_CTRL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `SAMPLE_CTRL` writer"]
pub struct W(crate::W<SAMPLE_CTRL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<SAMPLE_CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<SAMPLE_CTRL_SPEC>> for W {
    fn from(writer: crate::W<SAMPLE_CTRL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit).\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SUB_RESOLUTION_A {
    #[doc = "0: No description available"]
    CY8B = 0,
    #[doc = "1: No description available"]
    CY10B = 1,
}
impl From<SUB_RESOLUTION_A> for bool {
    #[inline(always)]
    fn from(variant: SUB_RESOLUTION_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SUB_RESOLUTION` reader - Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)."]
pub struct SUB_RESOLUTION_R(crate::FieldReader<bool, SUB_RESOLUTION_A>);
impl SUB_RESOLUTION_R {
    pub(crate) fn new(bits: bool) -> Self {
        SUB_RESOLUTION_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SUB_RESOLUTION_A {
        match self.bits {
            false => SUB_RESOLUTION_A::CY8B,
            true => SUB_RESOLUTION_A::CY10B,
        }
    }
    #[doc = "Checks if the value of the field is `CY8B`"]
    #[inline(always)]
    pub fn is_cy8b(&self) -> bool {
        **self == SUB_RESOLUTION_A::CY8B
    }
    #[doc = "Checks if the value of the field is `CY10B`"]
    #[inline(always)]
    pub fn is_cy10b(&self) -> bool {
        **self == SUB_RESOLUTION_A::CY10B
    }
}
impl core::ops::Deref for SUB_RESOLUTION_R {
    type Target = crate::FieldReader<bool, SUB_RESOLUTION_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SUB_RESOLUTION` writer - Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)."]
pub struct SUB_RESOLUTION_W<'a> {
    w: &'a mut W,
}
impl<'a> SUB_RESOLUTION_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SUB_RESOLUTION_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn cy8b(self) -> &'a mut W {
        self.variant(SUB_RESOLUTION_A::CY8B)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn cy10b(self) -> &'a mut W {
        self.variant(SUB_RESOLUTION_A::CY10B)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
}
#[doc = "Field `LEFT_ALIGN` reader - Left align data in data\\[15:0\\], default data is right aligned in data\\[11:0\\], with sign extension to 16 bits if the channel is differential."]
pub struct LEFT_ALIGN_R(crate::FieldReader<bool, bool>);
impl LEFT_ALIGN_R {
    pub(crate) fn new(bits: bool) -> Self {
        LEFT_ALIGN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for LEFT_ALIGN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LEFT_ALIGN` writer - Left align data in data\\[15:0\\], default data is right aligned in data\\[11:0\\], with sign extension to 16 bits if the channel is differential."]
pub struct LEFT_ALIGN_W<'a> {
    w: &'a mut W,
}
impl<'a> LEFT_ALIGN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
        self.w
    }
}
#[doc = "Output data from a single ended conversion as a signed value\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SINGLE_ENDED_SIGNED_A {
    #[doc = "0: No description available"]
    UNSIGNED = 0,
    #[doc = "1: No description available"]
    SIGNED = 1,
}
impl From<SINGLE_ENDED_SIGNED_A> for bool {
    #[inline(always)]
    fn from(variant: SINGLE_ENDED_SIGNED_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SINGLE_ENDED_SIGNED` reader - Output data from a single ended conversion as a signed value"]
pub struct SINGLE_ENDED_SIGNED_R(crate::FieldReader<bool, SINGLE_ENDED_SIGNED_A>);
impl SINGLE_ENDED_SIGNED_R {
    pub(crate) fn new(bits: bool) -> Self {
        SINGLE_ENDED_SIGNED_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SINGLE_ENDED_SIGNED_A {
        match self.bits {
            false => SINGLE_ENDED_SIGNED_A::UNSIGNED,
            true => SINGLE_ENDED_SIGNED_A::SIGNED,
        }
    }
    #[doc = "Checks if the value of the field is `UNSIGNED`"]
    #[inline(always)]
    pub fn is_unsigned(&self) -> bool {
        **self == SINGLE_ENDED_SIGNED_A::UNSIGNED
    }
    #[doc = "Checks if the value of the field is `SIGNED`"]
    #[inline(always)]
    pub fn is_signed(&self) -> bool {
        **self == SINGLE_ENDED_SIGNED_A::SIGNED
    }
}
impl core::ops::Deref for SINGLE_ENDED_SIGNED_R {
    type Target = crate::FieldReader<bool, SINGLE_ENDED_SIGNED_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SINGLE_ENDED_SIGNED` writer - Output data from a single ended conversion as a signed value"]
pub struct SINGLE_ENDED_SIGNED_W<'a> {
    w: &'a mut W,
}
impl<'a> SINGLE_ENDED_SIGNED_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SINGLE_ENDED_SIGNED_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn unsigned(self) -> &'a mut W {
        self.variant(SINGLE_ENDED_SIGNED_A::UNSIGNED)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn signed(self) -> &'a mut W {
        self.variant(SINGLE_ENDED_SIGNED_A::SIGNED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
        self.w
    }
}
#[doc = "Output data from a differential conversion as a signed value\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIFFERENTIAL_SIGNED_A {
    #[doc = "0: No description available"]
    UNSIGNED = 0,
    #[doc = "1: No description available"]
    SIGNED = 1,
}
impl From<DIFFERENTIAL_SIGNED_A> for bool {
    #[inline(always)]
    fn from(variant: DIFFERENTIAL_SIGNED_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `DIFFERENTIAL_SIGNED` reader - Output data from a differential conversion as a signed value"]
pub struct DIFFERENTIAL_SIGNED_R(crate::FieldReader<bool, DIFFERENTIAL_SIGNED_A>);
impl DIFFERENTIAL_SIGNED_R {
    pub(crate) fn new(bits: bool) -> Self {
        DIFFERENTIAL_SIGNED_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> DIFFERENTIAL_SIGNED_A {
        match self.bits {
            false => DIFFERENTIAL_SIGNED_A::UNSIGNED,
            true => DIFFERENTIAL_SIGNED_A::SIGNED,
        }
    }
    #[doc = "Checks if the value of the field is `UNSIGNED`"]
    #[inline(always)]
    pub fn is_unsigned(&self) -> bool {
        **self == DIFFERENTIAL_SIGNED_A::UNSIGNED
    }
    #[doc = "Checks if the value of the field is `SIGNED`"]
    #[inline(always)]
    pub fn is_signed(&self) -> bool {
        **self == DIFFERENTIAL_SIGNED_A::SIGNED
    }
}
impl core::ops::Deref for DIFFERENTIAL_SIGNED_R {
    type Target = crate::FieldReader<bool, DIFFERENTIAL_SIGNED_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DIFFERENTIAL_SIGNED` writer - Output data from a differential conversion as a signed value"]
pub struct DIFFERENTIAL_SIGNED_W<'a> {
    w: &'a mut W,
}
impl<'a> DIFFERENTIAL_SIGNED_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DIFFERENTIAL_SIGNED_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn unsigned(self) -> &'a mut W {
        self.variant(DIFFERENTIAL_SIGNED_A::UNSIGNED)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn signed(self) -> &'a mut W {
        self.variant(DIFFERENTIAL_SIGNED_A::SIGNED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
        self.w
    }
}
#[doc = "Field `AVG_CNT` reader - Averaging Count for channels that have over sampling enabled (AVG_EN). A channel will be sampled back to back (1<<(AVG_CNT+1)) = \\[2..256\\]
times before the result is stored and the next enabled channel is sampled (1st order accumulate and dump filter).?If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3)."]
pub struct AVG_CNT_R(crate::FieldReader<u8, u8>);
impl AVG_CNT_R {
    pub(crate) fn new(bits: u8) -> Self {
        AVG_CNT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for AVG_CNT_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `AVG_CNT` writer - Averaging Count for channels that have over sampling enabled (AVG_EN). A channel will be sampled back to back (1<<(AVG_CNT+1)) = \\[2..256\\]
times before the result is stored and the next enabled channel is sampled (1st order accumulate and dump filter).?If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3)."]
pub struct AVG_CNT_W<'a> {
    w: &'a mut W,
}
impl<'a> AVG_CNT_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
        self.w
    }
}
#[doc = "Field `AVG_SHIFT` reader - Averaging shifting: after averaging the result is shifted right to fit in the sample resolution. For averaging the sample resolution is the highest resolution allowed by wounding."]
pub struct AVG_SHIFT_R(crate::FieldReader<bool, bool>);
impl AVG_SHIFT_R {
    pub(crate) fn new(bits: bool) -> Self {
        AVG_SHIFT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for AVG_SHIFT_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `AVG_SHIFT` writer - Averaging shifting: after averaging the result is shifted right to fit in the sample resolution. For averaging the sample resolution is the highest resolution allowed by wounding."]
pub struct AVG_SHIFT_W<'a> {
    w: &'a mut W,
}
impl<'a> AVG_SHIFT_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
        self.w
    }
}
#[doc = "Field `CONTINUOUS` reader - - 0: Wait for next FW_TRIGGER (one shot) or hardware (DSI) trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.?- 1: Continuously scan enabled channels, ignore triggers."]
pub struct CONTINUOUS_R(crate::FieldReader<bool, bool>);
impl CONTINUOUS_R {
    pub(crate) fn new(bits: bool) -> Self {
        CONTINUOUS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CONTINUOUS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CONTINUOUS` writer - - 0: Wait for next FW_TRIGGER (one shot) or hardware (DSI) trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.?- 1: Continuously scan enabled channels, ignore triggers."]
pub struct CONTINUOUS_W<'a> {
    w: &'a mut W,
}
impl<'a> CONTINUOUS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
        self.w
    }
}
#[doc = "Field `DSI_TRIGGER_EN` reader - - 0: firmware trigger only: disable hardware (DSI) trigger.?- 1: enable hardware (DSI) trigger (e.g. from TCPWM, GPIO or UDB)."]
pub struct DSI_TRIGGER_EN_R(crate::FieldReader<bool, bool>);
impl DSI_TRIGGER_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        DSI_TRIGGER_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DSI_TRIGGER_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DSI_TRIGGER_EN` writer - - 0: firmware trigger only: disable hardware (DSI) trigger.?- 1: enable hardware (DSI) trigger (e.g. from TCPWM, GPIO or UDB)."]
pub struct DSI_TRIGGER_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> DSI_TRIGGER_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
        self.w
    }
}
#[doc = "Field `DSI_TRIGGER_LEVEL` reader - - 0: DSI trigger signal is a pulse input, a positive edge detected on the DSI trigger signal triggers a new scan.?- 1: DSI trigger signal is a level input, as long as the DSI trigger signal remains high the SAR will do continuous scans."]
pub struct DSI_TRIGGER_LEVEL_R(crate::FieldReader<bool, bool>);
impl DSI_TRIGGER_LEVEL_R {
    pub(crate) fn new(bits: bool) -> Self {
        DSI_TRIGGER_LEVEL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DSI_TRIGGER_LEVEL_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DSI_TRIGGER_LEVEL` writer - - 0: DSI trigger signal is a pulse input, a positive edge detected on the DSI trigger signal triggers a new scan.?- 1: DSI trigger signal is a level input, as long as the DSI trigger signal remains high the SAR will do continuous scans."]
pub struct DSI_TRIGGER_LEVEL_W<'a> {
    w: &'a mut W,
}
impl<'a> DSI_TRIGGER_LEVEL_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
        self.w
    }
}
#[doc = "Field `DSI_SYNC_TRIGGER` reader - - 0: bypass clock domain synchronisation of the DSI trigger signal.?- 1: synchronize the DSI trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain."]
pub struct DSI_SYNC_TRIGGER_R(crate::FieldReader<bool, bool>);
impl DSI_SYNC_TRIGGER_R {
    pub(crate) fn new(bits: bool) -> Self {
        DSI_SYNC_TRIGGER_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DSI_SYNC_TRIGGER_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DSI_SYNC_TRIGGER` writer - - 0: bypass clock domain synchronisation of the DSI trigger signal.?- 1: synchronize the DSI trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain."]
pub struct DSI_SYNC_TRIGGER_W<'a> {
    w: &'a mut W,
}
impl<'a> DSI_SYNC_TRIGGER_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
        self.w
    }
}
#[doc = "Field `EOS_DSI_OUT_EN` reader - Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a pulse is send on the dsi_eos signal."]
pub struct EOS_DSI_OUT_EN_R(crate::FieldReader<bool, bool>);
impl EOS_DSI_OUT_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        EOS_DSI_OUT_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EOS_DSI_OUT_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EOS_DSI_OUT_EN` writer - Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a pulse is send on the dsi_eos signal."]
pub struct EOS_DSI_OUT_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> EOS_DSI_OUT_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bit 0 - Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)."]
    #[inline(always)]
    pub fn sub_resolution(&self) -> SUB_RESOLUTION_R {
        SUB_RESOLUTION_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Left align data in data\\[15:0\\], default data is right aligned in data\\[11:0\\], with sign extension to 16 bits if the channel is differential."]
    #[inline(always)]
    pub fn left_align(&self) -> LEFT_ALIGN_R {
        LEFT_ALIGN_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bit 2 - Output data from a single ended conversion as a signed value"]
    #[inline(always)]
    pub fn single_ended_signed(&self) -> SINGLE_ENDED_SIGNED_R {
        SINGLE_ENDED_SIGNED_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - Output data from a differential conversion as a signed value"]
    #[inline(always)]
    pub fn differential_signed(&self) -> DIFFERENTIAL_SIGNED_R {
        DIFFERENTIAL_SIGNED_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bits 4:6 - Averaging Count for channels that have over sampling enabled (AVG_EN). A channel will be sampled back to back (1<<(AVG_CNT+1)) = \\[2..256\\]
times before the result is stored and the next enabled channel is sampled (1st order accumulate and dump filter).?If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3)."]
    #[inline(always)]
    pub fn avg_cnt(&self) -> AVG_CNT_R {
        AVG_CNT_R::new(((self.bits >> 4) & 0x07) as u8)
    }
    #[doc = "Bit 7 - Averaging shifting: after averaging the result is shifted right to fit in the sample resolution. For averaging the sample resolution is the highest resolution allowed by wounding."]
    #[inline(always)]
    pub fn avg_shift(&self) -> AVG_SHIFT_R {
        AVG_SHIFT_R::new(((self.bits >> 7) & 0x01) != 0)
    }
    #[doc = "Bit 16 - - 0: Wait for next FW_TRIGGER (one shot) or hardware (DSI) trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.?- 1: Continuously scan enabled channels, ignore triggers."]
    #[inline(always)]
    pub fn continuous(&self) -> CONTINUOUS_R {
        CONTINUOUS_R::new(((self.bits >> 16) & 0x01) != 0)
    }
    #[doc = "Bit 17 - - 0: firmware trigger only: disable hardware (DSI) trigger.?- 1: enable hardware (DSI) trigger (e.g. from TCPWM, GPIO or UDB)."]
    #[inline(always)]
    pub fn dsi_trigger_en(&self) -> DSI_TRIGGER_EN_R {
        DSI_TRIGGER_EN_R::new(((self.bits >> 17) & 0x01) != 0)
    }
    #[doc = "Bit 18 - - 0: DSI trigger signal is a pulse input, a positive edge detected on the DSI trigger signal triggers a new scan.?- 1: DSI trigger signal is a level input, as long as the DSI trigger signal remains high the SAR will do continuous scans."]
    #[inline(always)]
    pub fn dsi_trigger_level(&self) -> DSI_TRIGGER_LEVEL_R {
        DSI_TRIGGER_LEVEL_R::new(((self.bits >> 18) & 0x01) != 0)
    }
    #[doc = "Bit 19 - - 0: bypass clock domain synchronisation of the DSI trigger signal.?- 1: synchronize the DSI trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain."]
    #[inline(always)]
    pub fn dsi_sync_trigger(&self) -> DSI_SYNC_TRIGGER_R {
        DSI_SYNC_TRIGGER_R::new(((self.bits >> 19) & 0x01) != 0)
    }
    #[doc = "Bit 31 - Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a pulse is send on the dsi_eos signal."]
    #[inline(always)]
    pub fn eos_dsi_out_en(&self) -> EOS_DSI_OUT_EN_R {
        EOS_DSI_OUT_EN_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)."]
    #[inline(always)]
    pub fn sub_resolution(&mut self) -> SUB_RESOLUTION_W {
        SUB_RESOLUTION_W { w: self }
    }
    #[doc = "Bit 1 - Left align data in data\\[15:0\\], default data is right aligned in data\\[11:0\\], with sign extension to 16 bits if the channel is differential."]
    #[inline(always)]
    pub fn left_align(&mut self) -> LEFT_ALIGN_W {
        LEFT_ALIGN_W { w: self }
    }
    #[doc = "Bit 2 - Output data from a single ended conversion as a signed value"]
    #[inline(always)]
    pub fn single_ended_signed(&mut self) -> SINGLE_ENDED_SIGNED_W {
        SINGLE_ENDED_SIGNED_W { w: self }
    }
    #[doc = "Bit 3 - Output data from a differential conversion as a signed value"]
    #[inline(always)]
    pub fn differential_signed(&mut self) -> DIFFERENTIAL_SIGNED_W {
        DIFFERENTIAL_SIGNED_W { w: self }
    }
    #[doc = "Bits 4:6 - Averaging Count for channels that have over sampling enabled (AVG_EN). A channel will be sampled back to back (1<<(AVG_CNT+1)) = \\[2..256\\]
times before the result is stored and the next enabled channel is sampled (1st order accumulate and dump filter).?If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3)."]
    #[inline(always)]
    pub fn avg_cnt(&mut self) -> AVG_CNT_W {
        AVG_CNT_W { w: self }
    }
    #[doc = "Bit 7 - Averaging shifting: after averaging the result is shifted right to fit in the sample resolution. For averaging the sample resolution is the highest resolution allowed by wounding."]
    #[inline(always)]
    pub fn avg_shift(&mut self) -> AVG_SHIFT_W {
        AVG_SHIFT_W { w: self }
    }
    #[doc = "Bit 16 - - 0: Wait for next FW_TRIGGER (one shot) or hardware (DSI) trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.?- 1: Continuously scan enabled channels, ignore triggers."]
    #[inline(always)]
    pub fn continuous(&mut self) -> CONTINUOUS_W {
        CONTINUOUS_W { w: self }
    }
    #[doc = "Bit 17 - - 0: firmware trigger only: disable hardware (DSI) trigger.?- 1: enable hardware (DSI) trigger (e.g. from TCPWM, GPIO or UDB)."]
    #[inline(always)]
    pub fn dsi_trigger_en(&mut self) -> DSI_TRIGGER_EN_W {
        DSI_TRIGGER_EN_W { w: self }
    }
    #[doc = "Bit 18 - - 0: DSI trigger signal is a pulse input, a positive edge detected on the DSI trigger signal triggers a new scan.?- 1: DSI trigger signal is a level input, as long as the DSI trigger signal remains high the SAR will do continuous scans."]
    #[inline(always)]
    pub fn dsi_trigger_level(&mut self) -> DSI_TRIGGER_LEVEL_W {
        DSI_TRIGGER_LEVEL_W { w: self }
    }
    #[doc = "Bit 19 - - 0: bypass clock domain synchronisation of the DSI trigger signal.?- 1: synchronize the DSI trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain."]
    #[inline(always)]
    pub fn dsi_sync_trigger(&mut self) -> DSI_SYNC_TRIGGER_W {
        DSI_SYNC_TRIGGER_W { w: self }
    }
    #[doc = "Bit 31 - Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a pulse is send on the dsi_eos signal."]
    #[inline(always)]
    pub fn eos_dsi_out_en(&mut self) -> EOS_DSI_OUT_EN_W {
        EOS_DSI_OUT_EN_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Sample control register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sample_ctrl](index.html) module"]
pub struct SAMPLE_CTRL_SPEC;
impl crate::RegisterSpec for SAMPLE_CTRL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [sample_ctrl::R](R) reader structure"]
impl crate::Readable for SAMPLE_CTRL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sample_ctrl::W](W) writer structure"]
impl crate::Writable for SAMPLE_CTRL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets SAMPLE_CTRL to value 0"]
impl crate::Resettable for SAMPLE_CTRL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
