#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - Divider command register"]
    pub div_cmd: crate::Reg<div_cmd::DIV_CMD_SPEC>,
    _reserved1: [u8; 252usize],
    #[doc = "0x100 - Programmable clock control register"]
    pub pclk_ctl0: crate::Reg<pclk_ctl0::PCLK_CTL0_SPEC>,
    #[doc = "0x104 - Programmable clock control register"]
    pub pclk_ctl1: crate::Reg<pclk_ctl1::PCLK_CTL1_SPEC>,
    #[doc = "0x108 - Programmable clock control register"]
    pub pclk_ctl2: crate::Reg<pclk_ctl2::PCLK_CTL2_SPEC>,
    #[doc = "0x10c - Programmable clock control register"]
    pub pclk_ctl3: crate::Reg<pclk_ctl3::PCLK_CTL3_SPEC>,
    #[doc = "0x110 - Programmable clock control register"]
    pub pclk_ctl4: crate::Reg<pclk_ctl4::PCLK_CTL4_SPEC>,
    #[doc = "0x114 - Programmable clock control register"]
    pub pclk_ctl5: crate::Reg<pclk_ctl5::PCLK_CTL5_SPEC>,
    #[doc = "0x118 - Programmable clock control register"]
    pub pclk_ctl6: crate::Reg<pclk_ctl6::PCLK_CTL6_SPEC>,
    #[doc = "0x11c - Programmable clock control register"]
    pub pclk_ctl7: crate::Reg<pclk_ctl7::PCLK_CTL7_SPEC>,
    #[doc = "0x120 - Programmable clock control register"]
    pub pclk_ctl8: crate::Reg<pclk_ctl8::PCLK_CTL8_SPEC>,
    #[doc = "0x124 - Programmable clock control register"]
    pub pclk_ctl9: crate::Reg<pclk_ctl9::PCLK_CTL9_SPEC>,
    #[doc = "0x128 - Programmable clock control register"]
    pub pclk_ctl10: crate::Reg<pclk_ctl10::PCLK_CTL10_SPEC>,
    #[doc = "0x12c - Programmable clock control register"]
    pub pclk_ctl11: crate::Reg<pclk_ctl11::PCLK_CTL11_SPEC>,
    #[doc = "0x130 - Programmable clock control register"]
    pub pclk_ctl12: crate::Reg<pclk_ctl12::PCLK_CTL12_SPEC>,
    #[doc = "0x134 - Programmable clock control register"]
    pub pclk_ctl13: crate::Reg<pclk_ctl13::PCLK_CTL13_SPEC>,
    #[doc = "0x138 - Programmable clock control register"]
    pub pclk_ctl14: crate::Reg<pclk_ctl14::PCLK_CTL14_SPEC>,
    #[doc = "0x13c - Programmable clock control register"]
    pub pclk_ctl15: crate::Reg<pclk_ctl15::PCLK_CTL15_SPEC>,
    #[doc = "0x140 - Programmable clock control register"]
    pub pclk_ctl16: crate::Reg<pclk_ctl16::PCLK_CTL16_SPEC>,
    #[doc = "0x144 - Programmable clock control register"]
    pub pclk_ctl17: crate::Reg<pclk_ctl17::PCLK_CTL17_SPEC>,
    #[doc = "0x148 - Programmable clock control register"]
    pub pclk_ctl18: crate::Reg<pclk_ctl18::PCLK_CTL18_SPEC>,
    #[doc = "0x14c - Programmable clock control register"]
    pub pclk_ctl19: crate::Reg<pclk_ctl19::PCLK_CTL19_SPEC>,
    #[doc = "0x150 - Programmable clock control register"]
    pub pclk_ctl20: crate::Reg<pclk_ctl20::PCLK_CTL20_SPEC>,
    #[doc = "0x154 - Programmable clock control register"]
    pub pclk_ctl21: crate::Reg<pclk_ctl21::PCLK_CTL21_SPEC>,
    #[doc = "0x158 - Programmable clock control register"]
    pub pclk_ctl22: crate::Reg<pclk_ctl22::PCLK_CTL22_SPEC>,
    #[doc = "0x15c - Programmable clock control register"]
    pub pclk_ctl23: crate::Reg<pclk_ctl23::PCLK_CTL23_SPEC>,
    #[doc = "0x160 - Programmable clock control register"]
    pub pclk_ctl24: crate::Reg<pclk_ctl24::PCLK_CTL24_SPEC>,
    _reserved26: [u8; 412usize],
    #[doc = "0x300 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl0: crate::Reg<div_16_ctl0::DIV_16_CTL0_SPEC>,
    #[doc = "0x304 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl1: crate::Reg<div_16_ctl1::DIV_16_CTL1_SPEC>,
    #[doc = "0x308 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl2: crate::Reg<div_16_ctl2::DIV_16_CTL2_SPEC>,
    #[doc = "0x30c - Divider control register (for 16.0 divider)"]
    pub div_16_ctl3: crate::Reg<div_16_ctl3::DIV_16_CTL3_SPEC>,
    #[doc = "0x310 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl4: crate::Reg<div_16_ctl4::DIV_16_CTL4_SPEC>,
    #[doc = "0x314 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl5: crate::Reg<div_16_ctl5::DIV_16_CTL5_SPEC>,
    #[doc = "0x318 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl6: crate::Reg<div_16_ctl6::DIV_16_CTL6_SPEC>,
    #[doc = "0x31c - Divider control register (for 16.0 divider)"]
    pub div_16_ctl7: crate::Reg<div_16_ctl7::DIV_16_CTL7_SPEC>,
    #[doc = "0x320 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl8: crate::Reg<div_16_ctl8::DIV_16_CTL8_SPEC>,
    #[doc = "0x324 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl9: crate::Reg<div_16_ctl9::DIV_16_CTL9_SPEC>,
    #[doc = "0x328 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl10: crate::Reg<div_16_ctl10::DIV_16_CTL10_SPEC>,
    #[doc = "0x32c - Divider control register (for 16.0 divider)"]
    pub div_16_ctl11: crate::Reg<div_16_ctl11::DIV_16_CTL11_SPEC>,
    #[doc = "0x330 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl12: crate::Reg<div_16_ctl12::DIV_16_CTL12_SPEC>,
    #[doc = "0x334 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl13: crate::Reg<div_16_ctl13::DIV_16_CTL13_SPEC>,
    #[doc = "0x338 - Divider control register (for 16.0 divider)"]
    pub div_16_ctl14: crate::Reg<div_16_ctl14::DIV_16_CTL14_SPEC>,
    #[doc = "0x33c - Divider control register (for 16.0 divider)"]
    pub div_16_ctl15: crate::Reg<div_16_ctl15::DIV_16_CTL15_SPEC>,
    _reserved42: [u8; 192usize],
    #[doc = "0x400 - Divider control register (for 16.5 divider)"]
    pub div_16_5_ctl0: crate::Reg<div_16_5_ctl0::DIV_16_5_CTL0_SPEC>,
    #[doc = "0x404 - Divider control register (for 16.5 divider)"]
    pub div_16_5_ctl1: crate::Reg<div_16_5_ctl1::DIV_16_5_CTL1_SPEC>,
    #[doc = "0x408 - Divider control register (for 16.5 divider)"]
    pub div_16_5_ctl2: crate::Reg<div_16_5_ctl2::DIV_16_5_CTL2_SPEC>,
    #[doc = "0x40c - Divider control register (for 16.5 divider)"]
    pub div_16_5_ctl3: crate::Reg<div_16_5_ctl3::DIV_16_5_CTL3_SPEC>,
    _reserved46: [u8; 240usize],
    #[doc = "0x500 - Divider control register (for 24.5 divider)"]
    pub div_24_5_ctl: crate::Reg<div_24_5_ctl::DIV_24_5_CTL_SPEC>,
    _reserved47: [u8; 252usize],
    #[doc = "0x600 - Trigger control register"]
    pub tr_ctl: crate::Reg<tr_ctl::TR_CTL_SPEC>,
}
#[doc = "DIV_CMD register accessor: an alias for `Reg<DIV_CMD_SPEC>`"]
pub type DIV_CMD = crate::Reg<div_cmd::DIV_CMD_SPEC>;
#[doc = "Divider command register"]
pub mod div_cmd;
#[doc = "PCLK_CTL0 register accessor: an alias for `Reg<PCLK_CTL0_SPEC>`"]
pub type PCLK_CTL0 = crate::Reg<pclk_ctl0::PCLK_CTL0_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl0;
#[doc = "PCLK_CTL1 register accessor: an alias for `Reg<PCLK_CTL1_SPEC>`"]
pub type PCLK_CTL1 = crate::Reg<pclk_ctl1::PCLK_CTL1_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl1;
#[doc = "PCLK_CTL2 register accessor: an alias for `Reg<PCLK_CTL2_SPEC>`"]
pub type PCLK_CTL2 = crate::Reg<pclk_ctl2::PCLK_CTL2_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl2;
#[doc = "PCLK_CTL3 register accessor: an alias for `Reg<PCLK_CTL3_SPEC>`"]
pub type PCLK_CTL3 = crate::Reg<pclk_ctl3::PCLK_CTL3_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl3;
#[doc = "PCLK_CTL4 register accessor: an alias for `Reg<PCLK_CTL4_SPEC>`"]
pub type PCLK_CTL4 = crate::Reg<pclk_ctl4::PCLK_CTL4_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl4;
#[doc = "PCLK_CTL5 register accessor: an alias for `Reg<PCLK_CTL5_SPEC>`"]
pub type PCLK_CTL5 = crate::Reg<pclk_ctl5::PCLK_CTL5_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl5;
#[doc = "PCLK_CTL6 register accessor: an alias for `Reg<PCLK_CTL6_SPEC>`"]
pub type PCLK_CTL6 = crate::Reg<pclk_ctl6::PCLK_CTL6_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl6;
#[doc = "PCLK_CTL7 register accessor: an alias for `Reg<PCLK_CTL7_SPEC>`"]
pub type PCLK_CTL7 = crate::Reg<pclk_ctl7::PCLK_CTL7_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl7;
#[doc = "PCLK_CTL8 register accessor: an alias for `Reg<PCLK_CTL8_SPEC>`"]
pub type PCLK_CTL8 = crate::Reg<pclk_ctl8::PCLK_CTL8_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl8;
#[doc = "PCLK_CTL9 register accessor: an alias for `Reg<PCLK_CTL9_SPEC>`"]
pub type PCLK_CTL9 = crate::Reg<pclk_ctl9::PCLK_CTL9_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl9;
#[doc = "PCLK_CTL10 register accessor: an alias for `Reg<PCLK_CTL10_SPEC>`"]
pub type PCLK_CTL10 = crate::Reg<pclk_ctl10::PCLK_CTL10_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl10;
#[doc = "PCLK_CTL11 register accessor: an alias for `Reg<PCLK_CTL11_SPEC>`"]
pub type PCLK_CTL11 = crate::Reg<pclk_ctl11::PCLK_CTL11_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl11;
#[doc = "PCLK_CTL12 register accessor: an alias for `Reg<PCLK_CTL12_SPEC>`"]
pub type PCLK_CTL12 = crate::Reg<pclk_ctl12::PCLK_CTL12_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl12;
#[doc = "PCLK_CTL13 register accessor: an alias for `Reg<PCLK_CTL13_SPEC>`"]
pub type PCLK_CTL13 = crate::Reg<pclk_ctl13::PCLK_CTL13_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl13;
#[doc = "PCLK_CTL14 register accessor: an alias for `Reg<PCLK_CTL14_SPEC>`"]
pub type PCLK_CTL14 = crate::Reg<pclk_ctl14::PCLK_CTL14_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl14;
#[doc = "PCLK_CTL15 register accessor: an alias for `Reg<PCLK_CTL15_SPEC>`"]
pub type PCLK_CTL15 = crate::Reg<pclk_ctl15::PCLK_CTL15_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl15;
#[doc = "PCLK_CTL16 register accessor: an alias for `Reg<PCLK_CTL16_SPEC>`"]
pub type PCLK_CTL16 = crate::Reg<pclk_ctl16::PCLK_CTL16_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl16;
#[doc = "PCLK_CTL17 register accessor: an alias for `Reg<PCLK_CTL17_SPEC>`"]
pub type PCLK_CTL17 = crate::Reg<pclk_ctl17::PCLK_CTL17_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl17;
#[doc = "PCLK_CTL18 register accessor: an alias for `Reg<PCLK_CTL18_SPEC>`"]
pub type PCLK_CTL18 = crate::Reg<pclk_ctl18::PCLK_CTL18_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl18;
#[doc = "PCLK_CTL19 register accessor: an alias for `Reg<PCLK_CTL19_SPEC>`"]
pub type PCLK_CTL19 = crate::Reg<pclk_ctl19::PCLK_CTL19_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl19;
#[doc = "PCLK_CTL20 register accessor: an alias for `Reg<PCLK_CTL20_SPEC>`"]
pub type PCLK_CTL20 = crate::Reg<pclk_ctl20::PCLK_CTL20_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl20;
#[doc = "PCLK_CTL21 register accessor: an alias for `Reg<PCLK_CTL21_SPEC>`"]
pub type PCLK_CTL21 = crate::Reg<pclk_ctl21::PCLK_CTL21_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl21;
#[doc = "PCLK_CTL22 register accessor: an alias for `Reg<PCLK_CTL22_SPEC>`"]
pub type PCLK_CTL22 = crate::Reg<pclk_ctl22::PCLK_CTL22_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl22;
#[doc = "PCLK_CTL23 register accessor: an alias for `Reg<PCLK_CTL23_SPEC>`"]
pub type PCLK_CTL23 = crate::Reg<pclk_ctl23::PCLK_CTL23_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl23;
#[doc = "PCLK_CTL24 register accessor: an alias for `Reg<PCLK_CTL24_SPEC>`"]
pub type PCLK_CTL24 = crate::Reg<pclk_ctl24::PCLK_CTL24_SPEC>;
#[doc = "Programmable clock control register"]
pub mod pclk_ctl24;
#[doc = "DIV_16_CTL0 register accessor: an alias for `Reg<DIV_16_CTL0_SPEC>`"]
pub type DIV_16_CTL0 = crate::Reg<div_16_ctl0::DIV_16_CTL0_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl0;
#[doc = "DIV_16_CTL1 register accessor: an alias for `Reg<DIV_16_CTL1_SPEC>`"]
pub type DIV_16_CTL1 = crate::Reg<div_16_ctl1::DIV_16_CTL1_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl1;
#[doc = "DIV_16_CTL2 register accessor: an alias for `Reg<DIV_16_CTL2_SPEC>`"]
pub type DIV_16_CTL2 = crate::Reg<div_16_ctl2::DIV_16_CTL2_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl2;
#[doc = "DIV_16_CTL3 register accessor: an alias for `Reg<DIV_16_CTL3_SPEC>`"]
pub type DIV_16_CTL3 = crate::Reg<div_16_ctl3::DIV_16_CTL3_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl3;
#[doc = "DIV_16_CTL4 register accessor: an alias for `Reg<DIV_16_CTL4_SPEC>`"]
pub type DIV_16_CTL4 = crate::Reg<div_16_ctl4::DIV_16_CTL4_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl4;
#[doc = "DIV_16_CTL5 register accessor: an alias for `Reg<DIV_16_CTL5_SPEC>`"]
pub type DIV_16_CTL5 = crate::Reg<div_16_ctl5::DIV_16_CTL5_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl5;
#[doc = "DIV_16_CTL6 register accessor: an alias for `Reg<DIV_16_CTL6_SPEC>`"]
pub type DIV_16_CTL6 = crate::Reg<div_16_ctl6::DIV_16_CTL6_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl6;
#[doc = "DIV_16_CTL7 register accessor: an alias for `Reg<DIV_16_CTL7_SPEC>`"]
pub type DIV_16_CTL7 = crate::Reg<div_16_ctl7::DIV_16_CTL7_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl7;
#[doc = "DIV_16_CTL8 register accessor: an alias for `Reg<DIV_16_CTL8_SPEC>`"]
pub type DIV_16_CTL8 = crate::Reg<div_16_ctl8::DIV_16_CTL8_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl8;
#[doc = "DIV_16_CTL9 register accessor: an alias for `Reg<DIV_16_CTL9_SPEC>`"]
pub type DIV_16_CTL9 = crate::Reg<div_16_ctl9::DIV_16_CTL9_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl9;
#[doc = "DIV_16_CTL10 register accessor: an alias for `Reg<DIV_16_CTL10_SPEC>`"]
pub type DIV_16_CTL10 = crate::Reg<div_16_ctl10::DIV_16_CTL10_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl10;
#[doc = "DIV_16_CTL11 register accessor: an alias for `Reg<DIV_16_CTL11_SPEC>`"]
pub type DIV_16_CTL11 = crate::Reg<div_16_ctl11::DIV_16_CTL11_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl11;
#[doc = "DIV_16_CTL12 register accessor: an alias for `Reg<DIV_16_CTL12_SPEC>`"]
pub type DIV_16_CTL12 = crate::Reg<div_16_ctl12::DIV_16_CTL12_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl12;
#[doc = "DIV_16_CTL13 register accessor: an alias for `Reg<DIV_16_CTL13_SPEC>`"]
pub type DIV_16_CTL13 = crate::Reg<div_16_ctl13::DIV_16_CTL13_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl13;
#[doc = "DIV_16_CTL14 register accessor: an alias for `Reg<DIV_16_CTL14_SPEC>`"]
pub type DIV_16_CTL14 = crate::Reg<div_16_ctl14::DIV_16_CTL14_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl14;
#[doc = "DIV_16_CTL15 register accessor: an alias for `Reg<DIV_16_CTL15_SPEC>`"]
pub type DIV_16_CTL15 = crate::Reg<div_16_ctl15::DIV_16_CTL15_SPEC>;
#[doc = "Divider control register (for 16.0 divider)"]
pub mod div_16_ctl15;
#[doc = "DIV_16_5_CTL0 register accessor: an alias for `Reg<DIV_16_5_CTL0_SPEC>`"]
pub type DIV_16_5_CTL0 = crate::Reg<div_16_5_ctl0::DIV_16_5_CTL0_SPEC>;
#[doc = "Divider control register (for 16.5 divider)"]
pub mod div_16_5_ctl0;
#[doc = "DIV_16_5_CTL1 register accessor: an alias for `Reg<DIV_16_5_CTL1_SPEC>`"]
pub type DIV_16_5_CTL1 = crate::Reg<div_16_5_ctl1::DIV_16_5_CTL1_SPEC>;
#[doc = "Divider control register (for 16.5 divider)"]
pub mod div_16_5_ctl1;
#[doc = "DIV_16_5_CTL2 register accessor: an alias for `Reg<DIV_16_5_CTL2_SPEC>`"]
pub type DIV_16_5_CTL2 = crate::Reg<div_16_5_ctl2::DIV_16_5_CTL2_SPEC>;
#[doc = "Divider control register (for 16.5 divider)"]
pub mod div_16_5_ctl2;
#[doc = "DIV_16_5_CTL3 register accessor: an alias for `Reg<DIV_16_5_CTL3_SPEC>`"]
pub type DIV_16_5_CTL3 = crate::Reg<div_16_5_ctl3::DIV_16_5_CTL3_SPEC>;
#[doc = "Divider control register (for 16.5 divider)"]
pub mod div_16_5_ctl3;
#[doc = "DIV_24_5_CTL register accessor: an alias for `Reg<DIV_24_5_CTL_SPEC>`"]
pub type DIV_24_5_CTL = crate::Reg<div_24_5_ctl::DIV_24_5_CTL_SPEC>;
#[doc = "Divider control register (for 24.5 divider)"]
pub mod div_24_5_ctl;
#[doc = "TR_CTL register accessor: an alias for `Reg<TR_CTL_SPEC>`"]
pub type TR_CTL = crate::Reg<tr_ctl::TR_CTL_SPEC>;
#[doc = "Trigger control register"]
pub mod tr_ctl;
