#[doc = "Register `MUX_SWITCH1` reader"]
pub struct R(crate::R<MUX_SWITCH1_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<MUX_SWITCH1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<MUX_SWITCH1_SPEC>> for R {
    fn from(reader: crate::R<MUX_SWITCH1_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `MUX_SWITCH1` writer"]
pub struct W(crate::W<MUX_SWITCH1_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<MUX_SWITCH1_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<MUX_SWITCH1_SPEC>> for W {
    fn from(writer: crate::W<MUX_SWITCH1_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `MUX_FW_P4_DFT_INP` writer - Firmware control: 0=open, 1=close switch between P4 pin and dft_inp signal. Write with '1' to set bit."]
pub struct MUX_FW_P4_DFT_INP_W<'a> {
    w: &'a mut W,
}
impl<'a> MUX_FW_P4_DFT_INP_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
}
#[doc = "Field `MUX_FW_P5_DFT_INM` writer - Firmware control: 0=open, 1=close switch between P5 pin and dft_inm signal. Write with '1' to set bit."]
pub struct MUX_FW_P5_DFT_INM_W<'a> {
    w: &'a mut W,
}
impl<'a> MUX_FW_P5_DFT_INM_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
        self.w
    }
}
#[doc = "Field `MUX_FW_ADFT0_SARBUS0` writer - Firmware control: 0=open, 1=close switch between adft0 signal and sarbus0 signal. Write with '1' to set bit."]
pub struct MUX_FW_ADFT0_SARBUS0_W<'a> {
    w: &'a mut W,
}
impl<'a> MUX_FW_ADFT0_SARBUS0_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
        self.w
    }
}
#[doc = "Field `MUX_FW_ADFT1_SARBUS1` writer - Firmware control: 0=open, 1=close switch between adft1 signal and sarbus1 signal. Write with '1' to set bit."]
pub struct MUX_FW_ADFT1_SARBUS1_W<'a> {
    w: &'a mut W,
}
impl<'a> MUX_FW_ADFT1_SARBUS1_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
        self.w
    }
}
impl W {
    #[doc = "Bit 0 - Firmware control: 0=open, 1=close switch between P4 pin and dft_inp signal. Write with '1' to set bit."]
    #[inline(always)]
    pub fn mux_fw_p4_dft_inp(&mut self) -> MUX_FW_P4_DFT_INP_W {
        MUX_FW_P4_DFT_INP_W { w: self }
    }
    #[doc = "Bit 1 - Firmware control: 0=open, 1=close switch between P5 pin and dft_inm signal. Write with '1' to set bit."]
    #[inline(always)]
    pub fn mux_fw_p5_dft_inm(&mut self) -> MUX_FW_P5_DFT_INM_W {
        MUX_FW_P5_DFT_INM_W { w: self }
    }
    #[doc = "Bit 2 - Firmware control: 0=open, 1=close switch between adft0 signal and sarbus0 signal. Write with '1' to set bit."]
    #[inline(always)]
    pub fn mux_fw_adft0_sarbus0(&mut self) -> MUX_FW_ADFT0_SARBUS0_W {
        MUX_FW_ADFT0_SARBUS0_W { w: self }
    }
    #[doc = "Bit 3 - Firmware control: 0=open, 1=close switch between adft1 signal and sarbus1 signal. Write with '1' to set bit."]
    #[inline(always)]
    pub fn mux_fw_adft1_sarbus1(&mut self) -> MUX_FW_ADFT1_SARBUS1_W {
        MUX_FW_ADFT1_SARBUS1_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "SARMUX Firmware switch controls\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mux_switch1](index.html) module"]
pub struct MUX_SWITCH1_SPEC;
impl crate::RegisterSpec for MUX_SWITCH1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [mux_switch1::R](R) reader structure"]
impl crate::Readable for MUX_SWITCH1_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [mux_switch1::W](W) writer structure"]
impl crate::Writable for MUX_SWITCH1_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets MUX_SWITCH1 to value 0"]
impl crate::Resettable for MUX_SWITCH1_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
