#[doc = "Register `CFG30` reader"]
pub struct R(crate::R<CFG30_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG30_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG30_SPEC>> for R {
    fn from(reader: crate::R<CFG30_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG30` writer"]
pub struct W(crate::W<CFG30_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG30_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG30_SPEC>> for W {
    fn from(writer: crate::W<CFG30_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "The meaning of this bit depends on the value of ALT RES (CFG31). When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum RES_SEL_A {
    #[doc = "0: No description available"]
    RC_IN0 = 0,
    #[doc = "1: No description available"]
    RC_IN1 = 1,
    #[doc = "2: No description available"]
    RC_IN2 = 2,
    #[doc = "3: No description available"]
    RC_IN3 = 3,
}
impl From<RES_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: RES_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `RES_SEL` reader - The meaning of this bit depends on the value of ALT RES (CFG31). When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used."]
pub struct RES_SEL_R(crate::FieldReader<u8, RES_SEL_A>);
impl RES_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        RES_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RES_SEL_A {
        match self.bits {
            0 => RES_SEL_A::RC_IN0,
            1 => RES_SEL_A::RC_IN1,
            2 => RES_SEL_A::RC_IN2,
            3 => RES_SEL_A::RC_IN3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `RC_IN0`"]
    #[inline(always)]
    pub fn is_rc_in0(&self) -> bool {
        **self == RES_SEL_A::RC_IN0
    }
    #[doc = "Checks if the value of the field is `RC_IN1`"]
    #[inline(always)]
    pub fn is_rc_in1(&self) -> bool {
        **self == RES_SEL_A::RC_IN1
    }
    #[doc = "Checks if the value of the field is `RC_IN2`"]
    #[inline(always)]
    pub fn is_rc_in2(&self) -> bool {
        **self == RES_SEL_A::RC_IN2
    }
    #[doc = "Checks if the value of the field is `RC_IN3`"]
    #[inline(always)]
    pub fn is_rc_in3(&self) -> bool {
        **self == RES_SEL_A::RC_IN3
    }
}
impl core::ops::Deref for RES_SEL_R {
    type Target = crate::FieldReader<u8, RES_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RES_SEL` writer - The meaning of this bit depends on the value of ALT RES (CFG31). When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used."]
pub struct RES_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> RES_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RES_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in0(self) -> &'a mut W {
        self.variant(RES_SEL_A::RC_IN0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in1(self) -> &'a mut W {
        self.variant(RES_SEL_A::RC_IN1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in2(self) -> &'a mut W {
        self.variant(RES_SEL_A::RC_IN2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in3(self) -> &'a mut W {
        self.variant(RES_SEL_A::RC_IN3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
        self.w
    }
}
#[doc = "The meaning of this bit depends on the value of the ALT RES bit in CFG31. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RES_POL_A {
    #[doc = "0: No description available"]
    NEGATED = 0,
    #[doc = "1: No description available"]
    ASSERTED = 1,
}
impl From<RES_POL_A> for bool {
    #[inline(always)]
    fn from(variant: RES_POL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `RES_POL` reader - The meaning of this bit depends on the value of the ALT RES bit in CFG31. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused."]
pub struct RES_POL_R(crate::FieldReader<bool, RES_POL_A>);
impl RES_POL_R {
    pub(crate) fn new(bits: bool) -> Self {
        RES_POL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RES_POL_A {
        match self.bits {
            false => RES_POL_A::NEGATED,
            true => RES_POL_A::ASSERTED,
        }
    }
    #[doc = "Checks if the value of the field is `NEGATED`"]
    #[inline(always)]
    pub fn is_negated(&self) -> bool {
        **self == RES_POL_A::NEGATED
    }
    #[doc = "Checks if the value of the field is `ASSERTED`"]
    #[inline(always)]
    pub fn is_asserted(&self) -> bool {
        **self == RES_POL_A::ASSERTED
    }
}
impl core::ops::Deref for RES_POL_R {
    type Target = crate::FieldReader<bool, RES_POL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RES_POL` writer - The meaning of this bit depends on the value of the ALT RES bit in CFG31. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused."]
pub struct RES_POL_W<'a> {
    w: &'a mut W,
}
impl<'a> RES_POL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RES_POL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn negated(self) -> &'a mut W {
        self.variant(RES_POL_A::NEGATED)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn asserted(self) -> &'a mut W {
        self.variant(RES_POL_A::ASSERTED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
        self.w
    }
}
#[doc = "This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EN_RES_CNTCTL_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<EN_RES_CNTCTL_A> for bool {
    #[inline(always)]
    fn from(variant: EN_RES_CNTCTL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `EN_RES_CNTCTL` reader - This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also."]
pub struct EN_RES_CNTCTL_R(crate::FieldReader<bool, EN_RES_CNTCTL_A>);
impl EN_RES_CNTCTL_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_RES_CNTCTL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EN_RES_CNTCTL_A {
        match self.bits {
            false => EN_RES_CNTCTL_A::DISABLE,
            true => EN_RES_CNTCTL_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == EN_RES_CNTCTL_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == EN_RES_CNTCTL_A::ENABLE
    }
}
impl core::ops::Deref for EN_RES_CNTCTL_R {
    type Target = crate::FieldReader<bool, EN_RES_CNTCTL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_RES_CNTCTL` writer - This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also."]
pub struct EN_RES_CNTCTL_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_RES_CNTCTL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EN_RES_CNTCTL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(EN_RES_CNTCTL_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(EN_RES_CNTCTL_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3);
        self.w
    }
}
#[doc = "Enable global write operation for the configuration and working registers in this UDB. When this bit is set, the UDB ID select decoding is bypassed.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GUDB_WR_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<GUDB_WR_A> for bool {
    #[inline(always)]
    fn from(variant: GUDB_WR_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `GUDB_WR` reader - Enable global write operation for the configuration and working registers in this UDB. When this bit is set, the UDB ID select decoding is bypassed."]
pub struct GUDB_WR_R(crate::FieldReader<bool, GUDB_WR_A>);
impl GUDB_WR_R {
    pub(crate) fn new(bits: bool) -> Self {
        GUDB_WR_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> GUDB_WR_A {
        match self.bits {
            false => GUDB_WR_A::DISABLE,
            true => GUDB_WR_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == GUDB_WR_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == GUDB_WR_A::ENABLE
    }
}
impl core::ops::Deref for GUDB_WR_R {
    type Target = crate::FieldReader<bool, GUDB_WR_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `GUDB_WR` writer - Enable global write operation for the configuration and working registers in this UDB. When this bit is set, the UDB ID select decoding is bypassed."]
pub struct GUDB_WR_W<'a> {
    w: &'a mut W,
}
impl<'a> GUDB_WR_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: GUDB_WR_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(GUDB_WR_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(GUDB_WR_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4);
        self.w
    }
}
#[doc = "Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected Datapath routed reset.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DP_RES_POL_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<DP_RES_POL_A> for bool {
    #[inline(always)]
    fn from(variant: DP_RES_POL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `DP_RES_POL` reader - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected Datapath routed reset."]
pub struct DP_RES_POL_R(crate::FieldReader<bool, DP_RES_POL_A>);
impl DP_RES_POL_R {
    pub(crate) fn new(bits: bool) -> Self {
        DP_RES_POL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> DP_RES_POL_A {
        match self.bits {
            false => DP_RES_POL_A::NOINV,
            true => DP_RES_POL_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == DP_RES_POL_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == DP_RES_POL_A::INVERT
    }
}
impl core::ops::Deref for DP_RES_POL_R {
    type Target = crate::FieldReader<bool, DP_RES_POL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DP_RES_POL` writer - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected Datapath routed reset."]
pub struct DP_RES_POL_W<'a> {
    w: &'a mut W,
}
impl<'a> DP_RES_POL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DP_RES_POL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(DP_RES_POL_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(DP_RES_POL_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
        self.w
    }
}
#[doc = "Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected SC routed reset.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SC_RES_POL_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<SC_RES_POL_A> for bool {
    #[inline(always)]
    fn from(variant: SC_RES_POL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SC_RES_POL` reader - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected SC routed reset."]
pub struct SC_RES_POL_R(crate::FieldReader<bool, SC_RES_POL_A>);
impl SC_RES_POL_R {
    pub(crate) fn new(bits: bool) -> Self {
        SC_RES_POL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SC_RES_POL_A {
        match self.bits {
            false => SC_RES_POL_A::NOINV,
            true => SC_RES_POL_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == SC_RES_POL_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == SC_RES_POL_A::INVERT
    }
}
impl core::ops::Deref for SC_RES_POL_R {
    type Target = crate::FieldReader<bool, SC_RES_POL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SC_RES_POL` writer - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected SC routed reset."]
pub struct SC_RES_POL_W<'a> {
    w: &'a mut W,
}
impl<'a> SC_RES_POL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SC_RES_POL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(SC_RES_POL_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(SC_RES_POL_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - The meaning of this bit depends on the value of ALT RES (CFG31). When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used."]
    #[inline(always)]
    pub fn res_sel(&self) -> RES_SEL_R {
        RES_SEL_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bit 2 - The meaning of this bit depends on the value of the ALT RES bit in CFG31. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused."]
    #[inline(always)]
    pub fn res_pol(&self) -> RES_POL_R {
        RES_POL_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also."]
    #[inline(always)]
    pub fn en_res_cntctl(&self) -> EN_RES_CNTCTL_R {
        EN_RES_CNTCTL_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 4 - Enable global write operation for the configuration and working registers in this UDB. When this bit is set, the UDB ID select decoding is bypassed."]
    #[inline(always)]
    pub fn gudb_wr(&self) -> GUDB_WR_R {
        GUDB_WR_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 6 - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected Datapath routed reset."]
    #[inline(always)]
    pub fn dp_res_pol(&self) -> DP_RES_POL_R {
        DP_RES_POL_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected SC routed reset."]
    #[inline(always)]
    pub fn sc_res_pol(&self) -> SC_RES_POL_R {
        SC_RES_POL_R::new(((self.bits >> 7) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1 - The meaning of this bit depends on the value of ALT RES (CFG31). When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used."]
    #[inline(always)]
    pub fn res_sel(&mut self) -> RES_SEL_W {
        RES_SEL_W { w: self }
    }
    #[doc = "Bit 2 - The meaning of this bit depends on the value of the ALT RES bit in CFG31. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused."]
    #[inline(always)]
    pub fn res_pol(&mut self) -> RES_POL_W {
        RES_POL_W { w: self }
    }
    #[doc = "Bit 3 - This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also."]
    #[inline(always)]
    pub fn en_res_cntctl(&mut self) -> EN_RES_CNTCTL_W {
        EN_RES_CNTCTL_W { w: self }
    }
    #[doc = "Bit 4 - Enable global write operation for the configuration and working registers in this UDB. When this bit is set, the UDB ID select decoding is bypassed."]
    #[inline(always)]
    pub fn gudb_wr(&mut self) -> GUDB_WR_W {
        GUDB_WR_W { w: self }
    }
    #[doc = "Bit 6 - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected Datapath routed reset."]
    #[inline(always)]
    pub fn dp_res_pol(&mut self) -> DP_RES_POL_W {
        DP_RES_POL_W { w: self }
    }
    #[doc = "Bit 7 - Only valid when ALT RES (CFG31) is '1'. This bit controls the polarity of the selected SC routed reset."]
    #[inline(always)]
    pub fn sc_res_pol(&mut self) -> SC_RES_POL_W {
        SC_RES_POL_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Reset control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg30](index.html) module"]
pub struct CFG30_SPEC;
impl crate::RegisterSpec for CFG30_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg30::R](R) reader structure"]
impl crate::Readable for CFG30_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg30::W](W) writer structure"]
impl crate::Writable for CFG30_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG30 to value 0"]
impl crate::Resettable for CFG30_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
