#[doc = "Register `CFG16` reader"]
pub struct R(crate::R<CFG16_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG16_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG16_SPEC>> for R {
    fn from(reader: crate::R<CFG16_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG16` writer"]
pub struct W(crate::W<CFG16_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG16_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG16_SPEC>> for W {
    fn from(writer: crate::W<CFG16_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Datapath register access mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WRK16_CONCAT_A {
    #[doc = "0: No description available"]
    DEFAULT = 0,
    #[doc = "1: No description available"]
    CONCATENATE = 1,
}
impl From<WRK16_CONCAT_A> for bool {
    #[inline(always)]
    fn from(variant: WRK16_CONCAT_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `WRK16_CONCAT` reader - Datapath register access mode"]
pub struct WRK16_CONCAT_R(crate::FieldReader<bool, WRK16_CONCAT_A>);
impl WRK16_CONCAT_R {
    pub(crate) fn new(bits: bool) -> Self {
        WRK16_CONCAT_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> WRK16_CONCAT_A {
        match self.bits {
            false => WRK16_CONCAT_A::DEFAULT,
            true => WRK16_CONCAT_A::CONCATENATE,
        }
    }
    #[doc = "Checks if the value of the field is `DEFAULT`"]
    #[inline(always)]
    pub fn is_default(&self) -> bool {
        **self == WRK16_CONCAT_A::DEFAULT
    }
    #[doc = "Checks if the value of the field is `CONCATENATE`"]
    #[inline(always)]
    pub fn is_concatenate(&self) -> bool {
        **self == WRK16_CONCAT_A::CONCATENATE
    }
}
impl core::ops::Deref for WRK16_CONCAT_R {
    type Target = crate::FieldReader<bool, WRK16_CONCAT_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `WRK16_CONCAT` writer - Datapath register access mode"]
pub struct WRK16_CONCAT_W<'a> {
    w: &'a mut W,
}
impl<'a> WRK16_CONCAT_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: WRK16_CONCAT_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn default(self) -> &'a mut W {
        self.variant(WRK16_CONCAT_A::DEFAULT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn concatenate(self) -> &'a mut W {
        self.variant(WRK16_CONCAT_A::CONCATENATE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01);
        self.w
    }
}
#[doc = "External CRC/PRS mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXT_CRCPRS_A {
    #[doc = "0: No description available"]
    INTERNAL = 0,
    #[doc = "1: No description available"]
    EXTERNAL = 1,
}
impl From<EXT_CRCPRS_A> for bool {
    #[inline(always)]
    fn from(variant: EXT_CRCPRS_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `EXT_CRCPRS` reader - External CRC/PRS mode"]
pub struct EXT_CRCPRS_R(crate::FieldReader<bool, EXT_CRCPRS_A>);
impl EXT_CRCPRS_R {
    pub(crate) fn new(bits: bool) -> Self {
        EXT_CRCPRS_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EXT_CRCPRS_A {
        match self.bits {
            false => EXT_CRCPRS_A::INTERNAL,
            true => EXT_CRCPRS_A::EXTERNAL,
        }
    }
    #[doc = "Checks if the value of the field is `INTERNAL`"]
    #[inline(always)]
    pub fn is_internal(&self) -> bool {
        **self == EXT_CRCPRS_A::INTERNAL
    }
    #[doc = "Checks if the value of the field is `EXTERNAL`"]
    #[inline(always)]
    pub fn is_external(&self) -> bool {
        **self == EXT_CRCPRS_A::EXTERNAL
    }
}
impl core::ops::Deref for EXT_CRCPRS_R {
    type Target = crate::FieldReader<bool, EXT_CRCPRS_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EXT_CRCPRS` writer - External CRC/PRS mode"]
pub struct EXT_CRCPRS_W<'a> {
    w: &'a mut W,
}
impl<'a> EXT_CRCPRS_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EXT_CRCPRS_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn internal(self) -> &'a mut W {
        self.variant(EXT_CRCPRS_A::INTERNAL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn external(self) -> &'a mut W {
        self.variant(EXT_CRCPRS_A::EXTERNAL)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1);
        self.w
    }
}
#[doc = "Asynchronous FIFO clocking support\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIFO_ASYNC_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<FIFO_ASYNC_A> for bool {
    #[inline(always)]
    fn from(variant: FIFO_ASYNC_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `FIFO_ASYNC` reader - Asynchronous FIFO clocking support"]
pub struct FIFO_ASYNC_R(crate::FieldReader<bool, FIFO_ASYNC_A>);
impl FIFO_ASYNC_R {
    pub(crate) fn new(bits: bool) -> Self {
        FIFO_ASYNC_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> FIFO_ASYNC_A {
        match self.bits {
            false => FIFO_ASYNC_A::DISABLE,
            true => FIFO_ASYNC_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == FIFO_ASYNC_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == FIFO_ASYNC_A::ENABLE
    }
}
impl core::ops::Deref for FIFO_ASYNC_R {
    type Target = crate::FieldReader<bool, FIFO_ASYNC_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FIFO_ASYNC` writer - Asynchronous FIFO clocking support"]
pub struct FIFO_ASYNC_W<'a> {
    w: &'a mut W,
}
impl<'a> FIFO_ASYNC_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FIFO_ASYNC_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(FIFO_ASYNC_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(FIFO_ASYNC_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
        self.w
    }
}
#[doc = "Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIFO_EDGE_A {
    #[doc = "0: No description available"]
    LEVEL = 0,
    #[doc = "1: No description available"]
    EDGE = 1,
}
impl From<FIFO_EDGE_A> for bool {
    #[inline(always)]
    fn from(variant: FIFO_EDGE_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `FIFO_EDGE` reader - Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode"]
pub struct FIFO_EDGE_R(crate::FieldReader<bool, FIFO_EDGE_A>);
impl FIFO_EDGE_R {
    pub(crate) fn new(bits: bool) -> Self {
        FIFO_EDGE_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> FIFO_EDGE_A {
        match self.bits {
            false => FIFO_EDGE_A::LEVEL,
            true => FIFO_EDGE_A::EDGE,
        }
    }
    #[doc = "Checks if the value of the field is `LEVEL`"]
    #[inline(always)]
    pub fn is_level(&self) -> bool {
        **self == FIFO_EDGE_A::LEVEL
    }
    #[doc = "Checks if the value of the field is `EDGE`"]
    #[inline(always)]
    pub fn is_edge(&self) -> bool {
        **self == FIFO_EDGE_A::EDGE
    }
}
impl core::ops::Deref for FIFO_EDGE_R {
    type Target = crate::FieldReader<bool, FIFO_EDGE_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FIFO_EDGE` writer - Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode"]
pub struct FIFO_EDGE_W<'a> {
    w: &'a mut W,
}
impl<'a> FIFO_EDGE_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FIFO_EDGE_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn level(self) -> &'a mut W {
        self.variant(FIFO_EDGE_A::LEVEL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn edge(self) -> &'a mut W {
        self.variant(FIFO_EDGE_A::EDGE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3);
        self.w
    }
}
#[doc = "FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIFO_CAP_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<FIFO_CAP_A> for bool {
    #[inline(always)]
    fn from(variant: FIFO_CAP_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `FIFO_CAP` reader - FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture"]
pub struct FIFO_CAP_R(crate::FieldReader<bool, FIFO_CAP_A>);
impl FIFO_CAP_R {
    pub(crate) fn new(bits: bool) -> Self {
        FIFO_CAP_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> FIFO_CAP_A {
        match self.bits {
            false => FIFO_CAP_A::DISABLE,
            true => FIFO_CAP_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == FIFO_CAP_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == FIFO_CAP_A::ENABLE
    }
}
impl core::ops::Deref for FIFO_CAP_R {
    type Target = crate::FieldReader<bool, FIFO_CAP_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FIFO_CAP` writer - FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture"]
pub struct FIFO_CAP_W<'a> {
    w: &'a mut W,
}
impl<'a> FIFO_CAP_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FIFO_CAP_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(FIFO_CAP_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(FIFO_CAP_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4);
        self.w
    }
}
#[doc = "FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIFO_FAST_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<FIFO_FAST_A> for bool {
    #[inline(always)]
    fn from(variant: FIFO_FAST_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `FIFO_FAST` reader - FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power."]
pub struct FIFO_FAST_R(crate::FieldReader<bool, FIFO_FAST_A>);
impl FIFO_FAST_R {
    pub(crate) fn new(bits: bool) -> Self {
        FIFO_FAST_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> FIFO_FAST_A {
        match self.bits {
            false => FIFO_FAST_A::DISABLE,
            true => FIFO_FAST_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == FIFO_FAST_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == FIFO_FAST_A::ENABLE
    }
}
impl core::ops::Deref for FIFO_FAST_R {
    type Target = crate::FieldReader<bool, FIFO_FAST_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FIFO_FAST` writer - FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power."]
pub struct FIFO_FAST_W<'a> {
    w: &'a mut W,
}
impl<'a> FIFO_FAST_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FIFO_FAST_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(FIFO_FAST_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(FIFO_FAST_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5);
        self.w
    }
}
#[doc = "FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum F0_CK_INV_A {
    #[doc = "0: No description available"]
    NORMAL = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<F0_CK_INV_A> for bool {
    #[inline(always)]
    fn from(variant: F0_CK_INV_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `F0_CK_INV` reader - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
pub struct F0_CK_INV_R(crate::FieldReader<bool, F0_CK_INV_A>);
impl F0_CK_INV_R {
    pub(crate) fn new(bits: bool) -> Self {
        F0_CK_INV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> F0_CK_INV_A {
        match self.bits {
            false => F0_CK_INV_A::NORMAL,
            true => F0_CK_INV_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NORMAL`"]
    #[inline(always)]
    pub fn is_normal(&self) -> bool {
        **self == F0_CK_INV_A::NORMAL
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == F0_CK_INV_A::INVERT
    }
}
impl core::ops::Deref for F0_CK_INV_R {
    type Target = crate::FieldReader<bool, F0_CK_INV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `F0_CK_INV` writer - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
pub struct F0_CK_INV_W<'a> {
    w: &'a mut W,
}
impl<'a> F0_CK_INV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: F0_CK_INV_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn normal(self) -> &'a mut W {
        self.variant(F0_CK_INV_A::NORMAL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(F0_CK_INV_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
        self.w
    }
}
#[doc = "FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum F1_CK_INV_A {
    #[doc = "0: No description available"]
    NORMAL = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<F1_CK_INV_A> for bool {
    #[inline(always)]
    fn from(variant: F1_CK_INV_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `F1_CK_INV` reader - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
pub struct F1_CK_INV_R(crate::FieldReader<bool, F1_CK_INV_A>);
impl F1_CK_INV_R {
    pub(crate) fn new(bits: bool) -> Self {
        F1_CK_INV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> F1_CK_INV_A {
        match self.bits {
            false => F1_CK_INV_A::NORMAL,
            true => F1_CK_INV_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NORMAL`"]
    #[inline(always)]
    pub fn is_normal(&self) -> bool {
        **self == F1_CK_INV_A::NORMAL
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == F1_CK_INV_A::INVERT
    }
}
impl core::ops::Deref for F1_CK_INV_R {
    type Target = crate::FieldReader<bool, F1_CK_INV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `F1_CK_INV` writer - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
pub struct F1_CK_INV_W<'a> {
    w: &'a mut W,
}
impl<'a> F1_CK_INV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: F1_CK_INV_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn normal(self) -> &'a mut W {
        self.variant(F1_CK_INV_A::NORMAL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(F1_CK_INV_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7);
        self.w
    }
}
impl R {
    #[doc = "Bit 0 - Datapath register access mode"]
    #[inline(always)]
    pub fn wrk16_concat(&self) -> WRK16_CONCAT_R {
        WRK16_CONCAT_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - External CRC/PRS mode"]
    #[inline(always)]
    pub fn ext_crcprs(&self) -> EXT_CRCPRS_R {
        EXT_CRCPRS_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bit 2 - Asynchronous FIFO clocking support"]
    #[inline(always)]
    pub fn fifo_async(&self) -> FIFO_ASYNC_R {
        FIFO_ASYNC_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode"]
    #[inline(always)]
    pub fn fifo_edge(&self) -> FIFO_EDGE_R {
        FIFO_EDGE_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 4 - FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture"]
    #[inline(always)]
    pub fn fifo_cap(&self) -> FIFO_CAP_R {
        FIFO_CAP_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 5 - FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power."]
    #[inline(always)]
    pub fn fifo_fast(&self) -> FIFO_FAST_R {
        FIFO_FAST_R::new(((self.bits >> 5) & 0x01) != 0)
    }
    #[doc = "Bit 6 - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
    #[inline(always)]
    pub fn f0_ck_inv(&self) -> F0_CK_INV_R {
        F0_CK_INV_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
    #[inline(always)]
    pub fn f1_ck_inv(&self) -> F1_CK_INV_R {
        F1_CK_INV_R::new(((self.bits >> 7) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Datapath register access mode"]
    #[inline(always)]
    pub fn wrk16_concat(&mut self) -> WRK16_CONCAT_W {
        WRK16_CONCAT_W { w: self }
    }
    #[doc = "Bit 1 - External CRC/PRS mode"]
    #[inline(always)]
    pub fn ext_crcprs(&mut self) -> EXT_CRCPRS_W {
        EXT_CRCPRS_W { w: self }
    }
    #[doc = "Bit 2 - Asynchronous FIFO clocking support"]
    #[inline(always)]
    pub fn fifo_async(&mut self) -> FIFO_ASYNC_W {
        FIFO_ASYNC_W { w: self }
    }
    #[doc = "Bit 3 - Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode"]
    #[inline(always)]
    pub fn fifo_edge(&mut self) -> FIFO_EDGE_W {
        FIFO_EDGE_W { w: self }
    }
    #[doc = "Bit 4 - FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture"]
    #[inline(always)]
    pub fn fifo_cap(&mut self) -> FIFO_CAP_W {
        FIFO_CAP_W { w: self }
    }
    #[doc = "Bit 5 - FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power."]
    #[inline(always)]
    pub fn fifo_fast(&mut self) -> FIFO_FAST_W {
        FIFO_FAST_W { w: self }
    }
    #[doc = "Bit 6 - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
    #[inline(always)]
    pub fn f0_ck_inv(&mut self) -> F0_CK_INV_W {
        F0_CK_INV_W { w: self }
    }
    #[doc = "Bit 7 - FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock."]
    #[inline(always)]
    pub fn f1_ck_inv(&mut self) -> F1_CK_INV_W {
        F1_CK_INV_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Datapath FIFO and register access configuration control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg16](index.html) module"]
pub struct CFG16_SPEC;
impl crate::RegisterSpec for CFG16_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg16::R](R) reader structure"]
impl crate::Readable for CFG16_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg16::W](W) writer structure"]
impl crate::Writable for CFG16_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG16 to value 0"]
impl crate::Resettable for CFG16_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
