#[doc = "Register `PLL0_TRIM` reader"]
pub struct R(crate::R<PLL0_TRIM_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PLL0_TRIM_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PLL0_TRIM_SPEC>> for R {
    fn from(reader: crate::R<PLL0_TRIM_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PLL0_TRIM` writer"]
pub struct W(crate::W<PLL0_TRIM_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PLL0_TRIM_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PLL0_TRIM_SPEC>> for W {
    fn from(writer: crate::W<PLL0_TRIM_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `VCO_GAIN` reader - Programmable VCO frequency characteristic at high freq - set to <10>"]
pub struct VCO_GAIN_R(crate::FieldReader<u8, u8>);
impl VCO_GAIN_R {
    pub(crate) fn new(bits: u8) -> Self {
        VCO_GAIN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for VCO_GAIN_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `VCO_GAIN` writer - Programmable VCO frequency characteristic at high freq - set to <10>"]
pub struct VCO_GAIN_W<'a> {
    w: &'a mut W,
}
impl<'a> VCO_GAIN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
        self.w
    }
}
#[doc = "Selects the allowed phase error before declaring the PLL Unlocked\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum LOCK_WINDOW_A {
    #[doc = "0: No description available"]
    DELAY_25NS = 0,
    #[doc = "1: No description available"]
    DELAY_50NS = 1,
    #[doc = "2: No description available"]
    DELAY_75NS = 2,
    #[doc = "3: No description available"]
    DELAY_100NS = 3,
}
impl From<LOCK_WINDOW_A> for u8 {
    #[inline(always)]
    fn from(variant: LOCK_WINDOW_A) -> Self {
        variant as _
    }
}
#[doc = "Field `LOCK_WINDOW` reader - Selects the allowed phase error before declaring the PLL Unlocked"]
pub struct LOCK_WINDOW_R(crate::FieldReader<u8, LOCK_WINDOW_A>);
impl LOCK_WINDOW_R {
    pub(crate) fn new(bits: u8) -> Self {
        LOCK_WINDOW_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> LOCK_WINDOW_A {
        match self.bits {
            0 => LOCK_WINDOW_A::DELAY_25NS,
            1 => LOCK_WINDOW_A::DELAY_50NS,
            2 => LOCK_WINDOW_A::DELAY_75NS,
            3 => LOCK_WINDOW_A::DELAY_100NS,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `DELAY_25NS`"]
    #[inline(always)]
    pub fn is_delay_25ns(&self) -> bool {
        **self == LOCK_WINDOW_A::DELAY_25NS
    }
    #[doc = "Checks if the value of the field is `DELAY_50NS`"]
    #[inline(always)]
    pub fn is_delay_50ns(&self) -> bool {
        **self == LOCK_WINDOW_A::DELAY_50NS
    }
    #[doc = "Checks if the value of the field is `DELAY_75NS`"]
    #[inline(always)]
    pub fn is_delay_75ns(&self) -> bool {
        **self == LOCK_WINDOW_A::DELAY_75NS
    }
    #[doc = "Checks if the value of the field is `DELAY_100NS`"]
    #[inline(always)]
    pub fn is_delay_100ns(&self) -> bool {
        **self == LOCK_WINDOW_A::DELAY_100NS
    }
}
impl core::ops::Deref for LOCK_WINDOW_R {
    type Target = crate::FieldReader<u8, LOCK_WINDOW_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LOCK_WINDOW` writer - Selects the allowed phase error before declaring the PLL Unlocked"]
pub struct LOCK_WINDOW_W<'a> {
    w: &'a mut W,
}
impl<'a> LOCK_WINDOW_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: LOCK_WINDOW_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn delay_25ns(self) -> &'a mut W {
        self.variant(LOCK_WINDOW_A::DELAY_25NS)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn delay_50ns(self) -> &'a mut W {
        self.variant(LOCK_WINDOW_A::DELAY_50NS)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn delay_75ns(self) -> &'a mut W {
        self.variant(LOCK_WINDOW_A::DELAY_75NS)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn delay_100ns(self) -> &'a mut W {
        self.variant(LOCK_WINDOW_A::DELAY_100NS)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
        self.w
    }
}
#[doc = "Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum LOCK_DELAY_A {
    #[doc = "0: No description available"]
    PFD_CLK_16 = 0,
    #[doc = "1: No description available"]
    PFD_CLK_32 = 1,
    #[doc = "2: No description available"]
    PFD_CLK_48 = 2,
    #[doc = "3: No description available"]
    PFD_CLK_64 = 3,
}
impl From<LOCK_DELAY_A> for u8 {
    #[inline(always)]
    fn from(variant: LOCK_DELAY_A) -> Self {
        variant as _
    }
}
#[doc = "Field `LOCK_DELAY` reader - Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)"]
pub struct LOCK_DELAY_R(crate::FieldReader<u8, LOCK_DELAY_A>);
impl LOCK_DELAY_R {
    pub(crate) fn new(bits: u8) -> Self {
        LOCK_DELAY_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> LOCK_DELAY_A {
        match self.bits {
            0 => LOCK_DELAY_A::PFD_CLK_16,
            1 => LOCK_DELAY_A::PFD_CLK_32,
            2 => LOCK_DELAY_A::PFD_CLK_48,
            3 => LOCK_DELAY_A::PFD_CLK_64,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `PFD_CLK_16`"]
    #[inline(always)]
    pub fn is_pfd_clk_16(&self) -> bool {
        **self == LOCK_DELAY_A::PFD_CLK_16
    }
    #[doc = "Checks if the value of the field is `PFD_CLK_32`"]
    #[inline(always)]
    pub fn is_pfd_clk_32(&self) -> bool {
        **self == LOCK_DELAY_A::PFD_CLK_32
    }
    #[doc = "Checks if the value of the field is `PFD_CLK_48`"]
    #[inline(always)]
    pub fn is_pfd_clk_48(&self) -> bool {
        **self == LOCK_DELAY_A::PFD_CLK_48
    }
    #[doc = "Checks if the value of the field is `PFD_CLK_64`"]
    #[inline(always)]
    pub fn is_pfd_clk_64(&self) -> bool {
        **self == LOCK_DELAY_A::PFD_CLK_64
    }
}
impl core::ops::Deref for LOCK_DELAY_R {
    type Target = crate::FieldReader<u8, LOCK_DELAY_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LOCK_DELAY` writer - Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)"]
pub struct LOCK_DELAY_W<'a> {
    w: &'a mut W,
}
impl<'a> LOCK_DELAY_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: LOCK_DELAY_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pfd_clk_16(self) -> &'a mut W {
        self.variant(LOCK_DELAY_A::PFD_CLK_16)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pfd_clk_32(self) -> &'a mut W {
        self.variant(LOCK_DELAY_A::PFD_CLK_32)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pfd_clk_48(self) -> &'a mut W {
        self.variant(LOCK_DELAY_A::PFD_CLK_48)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pfd_clk_64(self) -> &'a mut W {
        self.variant(LOCK_DELAY_A::PFD_CLK_64)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - Programmable VCO frequency characteristic at high freq - set to <10>"]
    #[inline(always)]
    pub fn vco_gain(&self) -> VCO_GAIN_R {
        VCO_GAIN_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bits 2:3 - Selects the allowed phase error before declaring the PLL Unlocked"]
    #[inline(always)]
    pub fn lock_window(&self) -> LOCK_WINDOW_R {
        LOCK_WINDOW_R::new(((self.bits >> 2) & 0x03) as u8)
    }
    #[doc = "Bits 4:5 - Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)"]
    #[inline(always)]
    pub fn lock_delay(&self) -> LOCK_DELAY_R {
        LOCK_DELAY_R::new(((self.bits >> 4) & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bits 0:1 - Programmable VCO frequency characteristic at high freq - set to <10>"]
    #[inline(always)]
    pub fn vco_gain(&mut self) -> VCO_GAIN_W {
        VCO_GAIN_W { w: self }
    }
    #[doc = "Bits 2:3 - Selects the allowed phase error before declaring the PLL Unlocked"]
    #[inline(always)]
    pub fn lock_window(&mut self) -> LOCK_WINDOW_W {
        LOCK_WINDOW_W { w: self }
    }
    #[doc = "Bits 4:5 - Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)"]
    #[inline(always)]
    pub fn lock_delay(&mut self) -> LOCK_DELAY_W {
        LOCK_DELAY_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "PLL #0 Trim Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0_trim](index.html) module"]
pub struct PLL0_TRIM_SPEC;
impl crate::RegisterSpec for PLL0_TRIM_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pll0_trim::R](R) reader structure"]
impl crate::Readable for PLL0_TRIM_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pll0_trim::W](W) writer structure"]
impl crate::Writable for PLL0_TRIM_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PLL0_TRIM to value 0"]
impl crate::Resettable for PLL0_TRIM_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
