#[doc = "Register `PLL1_CONFIG` reader"]
pub struct R(crate::R<PLL1_CONFIG_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PLL1_CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PLL1_CONFIG_SPEC>> for R {
    fn from(reader: crate::R<PLL1_CONFIG_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PLL1_CONFIG` writer"]
pub struct W(crate::W<PLL1_CONFIG_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PLL1_CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PLL1_CONFIG_SPEC>> for W {
    fn from(writer: crate::W<PLL1_CONFIG_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `FEEDBACK_DIV` reader - Control bits for feedback divider: Valid divide is 8-256. Do not change while PLL output is selected."]
pub struct FEEDBACK_DIV_R(crate::FieldReader<u8, u8>);
impl FEEDBACK_DIV_R {
    pub(crate) fn new(bits: u8) -> Self {
        FEEDBACK_DIV_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for FEEDBACK_DIV_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FEEDBACK_DIV` writer - Control bits for feedback divider: Valid divide is 8-256. Do not change while PLL output is selected."]
pub struct FEEDBACK_DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> FEEDBACK_DIV_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
}
#[doc = "Field `REFERENCE_DIV` reader - Control bits for reference divider: Divide by 2=0001, ?, divide by 64=111111. Do not change while PLL output is selected."]
pub struct REFERENCE_DIV_R(crate::FieldReader<u8, u8>);
impl REFERENCE_DIV_R {
    pub(crate) fn new(bits: u8) -> Self {
        REFERENCE_DIV_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for REFERENCE_DIV_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `REFERENCE_DIV` writer - Control bits for reference divider: Divide by 2=0001, ?, divide by 64=111111. Do not change while PLL output is selected."]
pub struct REFERENCE_DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> REFERENCE_DIV_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8);
        self.w
    }
}
#[doc = "Control bits for Output divider. Do not change while PLL output is selected.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum OUTPUT_DIV_A {
    #[doc = "0: No description available"]
    PASS = 0,
    #[doc = "1: No description available"]
    DIV2 = 1,
    #[doc = "2: No description available"]
    DIV4 = 2,
    #[doc = "3: No description available"]
    DIV8 = 3,
}
impl From<OUTPUT_DIV_A> for u8 {
    #[inline(always)]
    fn from(variant: OUTPUT_DIV_A) -> Self {
        variant as _
    }
}
#[doc = "Field `OUTPUT_DIV` reader - Control bits for Output divider. Do not change while PLL output is selected."]
pub struct OUTPUT_DIV_R(crate::FieldReader<u8, OUTPUT_DIV_A>);
impl OUTPUT_DIV_R {
    pub(crate) fn new(bits: u8) -> Self {
        OUTPUT_DIV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> OUTPUT_DIV_A {
        match self.bits {
            0 => OUTPUT_DIV_A::PASS,
            1 => OUTPUT_DIV_A::DIV2,
            2 => OUTPUT_DIV_A::DIV4,
            3 => OUTPUT_DIV_A::DIV8,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `PASS`"]
    #[inline(always)]
    pub fn is_pass(&self) -> bool {
        **self == OUTPUT_DIV_A::PASS
    }
    #[doc = "Checks if the value of the field is `DIV2`"]
    #[inline(always)]
    pub fn is_div2(&self) -> bool {
        **self == OUTPUT_DIV_A::DIV2
    }
    #[doc = "Checks if the value of the field is `DIV4`"]
    #[inline(always)]
    pub fn is_div4(&self) -> bool {
        **self == OUTPUT_DIV_A::DIV4
    }
    #[doc = "Checks if the value of the field is `DIV8`"]
    #[inline(always)]
    pub fn is_div8(&self) -> bool {
        **self == OUTPUT_DIV_A::DIV8
    }
}
impl core::ops::Deref for OUTPUT_DIV_R {
    type Target = crate::FieldReader<u8, OUTPUT_DIV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `OUTPUT_DIV` writer - Control bits for Output divider. Do not change while PLL output is selected."]
pub struct OUTPUT_DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> OUTPUT_DIV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: OUTPUT_DIV_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pass(self) -> &'a mut W {
        self.variant(OUTPUT_DIV_A::PASS)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div2(self) -> &'a mut W {
        self.variant(OUTPUT_DIV_A::DIV2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div4(self) -> &'a mut W {
        self.variant(OUTPUT_DIV_A::DIV4)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div8(self) -> &'a mut W {
        self.variant(OUTPUT_DIV_A::DIV8)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14);
        self.w
    }
}
#[doc = "Field `ICP_SEL` reader - Programmable charge pump current between 0uA and 7uA. Do not change while the PLL output is selected. For functional operation, the value must be set according to the PLL output frequency Fout (measured before the output divider):?0: 0uA (Hi-Z) Engineering use only?1: 1uA. Engineering use only?2: 2uA. Use when Fout <= 67MHz?3: 3uA. Use when Fout > 67MHz?4-7: 4uA-7uA. Engineering use only"]
pub struct ICP_SEL_R(crate::FieldReader<u8, u8>);
impl ICP_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        ICP_SEL_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ICP_SEL_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ICP_SEL` writer - Programmable charge pump current between 0uA and 7uA. Do not change while the PLL output is selected. For functional operation, the value must be set according to the PLL output frequency Fout (measured before the output divider):?0: 0uA (Hi-Z) Engineering use only?1: 1uA. Engineering use only?2: 2uA. Use when Fout <= 67MHz?3: 3uA. Use when Fout > 67MHz?4-7: 4uA-7uA. Engineering use only"]
pub struct ICP_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> ICP_SEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
        self.w
    }
}
#[doc = "Selects the source of the system PLL1 clock.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum BYPASS_SEL_A {
    #[doc = "0: No description available"]
    AUTO = 0,
    #[doc = "1: No description available"]
    AUTO1 = 1,
    #[doc = "2: No description available"]
    PLL_REF = 2,
    #[doc = "3: No description available"]
    PLL_OUT = 3,
}
impl From<BYPASS_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: BYPASS_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `BYPASS_SEL` reader - Selects the source of the system PLL1 clock."]
pub struct BYPASS_SEL_R(crate::FieldReader<u8, BYPASS_SEL_A>);
impl BYPASS_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        BYPASS_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> BYPASS_SEL_A {
        match self.bits {
            0 => BYPASS_SEL_A::AUTO,
            1 => BYPASS_SEL_A::AUTO1,
            2 => BYPASS_SEL_A::PLL_REF,
            3 => BYPASS_SEL_A::PLL_OUT,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `AUTO`"]
    #[inline(always)]
    pub fn is_auto(&self) -> bool {
        **self == BYPASS_SEL_A::AUTO
    }
    #[doc = "Checks if the value of the field is `AUTO1`"]
    #[inline(always)]
    pub fn is_auto1(&self) -> bool {
        **self == BYPASS_SEL_A::AUTO1
    }
    #[doc = "Checks if the value of the field is `PLL_REF`"]
    #[inline(always)]
    pub fn is_pll_ref(&self) -> bool {
        **self == BYPASS_SEL_A::PLL_REF
    }
    #[doc = "Checks if the value of the field is `PLL_OUT`"]
    #[inline(always)]
    pub fn is_pll_out(&self) -> bool {
        **self == BYPASS_SEL_A::PLL_OUT
    }
}
impl core::ops::Deref for BYPASS_SEL_R {
    type Target = crate::FieldReader<u8, BYPASS_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BYPASS_SEL` writer - Selects the source of the system PLL1 clock."]
pub struct BYPASS_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> BYPASS_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: BYPASS_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn auto(self) -> &'a mut W {
        self.variant(BYPASS_SEL_A::AUTO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn auto1(self) -> &'a mut W {
        self.variant(BYPASS_SEL_A::AUTO1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pll_ref(self) -> &'a mut W {
        self.variant(BYPASS_SEL_A::PLL_REF)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pll_out(self) -> &'a mut W {
        self.variant(BYPASS_SEL_A::PLL_OUT)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20);
        self.w
    }
}
#[doc = "Field `ISOLATE_N` reader - Isolation control of PLL outputs. This also internally resets the PLL. De-assert >= 5us after ENABLE=1. Assertion can happen in same write as ENABLE=0. Do not change while PLL output is selected.?0: Isolate outputs; Precharge PLL control voltage if PLL0_TEST.FAST_LOCK_EN is set to 1.?1: Do not isolate outputs"]
pub struct ISOLATE_N_R(crate::FieldReader<bool, bool>);
impl ISOLATE_N_R {
    pub(crate) fn new(bits: bool) -> Self {
        ISOLATE_N_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ISOLATE_N_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ISOLATE_N` writer - Isolation control of PLL outputs. This also internally resets the PLL. De-assert >= 5us after ENABLE=1. Assertion can happen in same write as ENABLE=0. Do not change while PLL output is selected.?0: Isolate outputs; Precharge PLL control voltage if PLL0_TEST.FAST_LOCK_EN is set to 1.?1: Do not isolate outputs"]
pub struct ISOLATE_N_W<'a> {
    w: &'a mut W,
}
impl<'a> ISOLATE_N_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
        self.w
    }
}
#[doc = "Field `ENABLE` reader - Master enable for PLL power gate. Refer to ISOLATE_N field for required sequencing.?0: Block is powered off?1: Block is powered on"]
pub struct ENABLE_R(crate::FieldReader<bool, bool>);
impl ENABLE_R {
    pub(crate) fn new(bits: bool) -> Self {
        ENABLE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ENABLE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ENABLE` writer - Master enable for PLL power gate. Refer to ISOLATE_N field for required sequencing.?0: Block is powered off?1: Block is powered on"]
pub struct ENABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> ENABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:7 - Control bits for feedback divider: Valid divide is 8-256. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn feedback_div(&self) -> FEEDBACK_DIV_R {
        FEEDBACK_DIV_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bits 8:13 - Control bits for reference divider: Divide by 2=0001, ?, divide by 64=111111. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn reference_div(&self) -> REFERENCE_DIV_R {
        REFERENCE_DIV_R::new(((self.bits >> 8) & 0x3f) as u8)
    }
    #[doc = "Bits 14:15 - Control bits for Output divider. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn output_div(&self) -> OUTPUT_DIV_R {
        OUTPUT_DIV_R::new(((self.bits >> 14) & 0x03) as u8)
    }
    #[doc = "Bits 16:18 - Programmable charge pump current between 0uA and 7uA. Do not change while the PLL output is selected. For functional operation, the value must be set according to the PLL output frequency Fout (measured before the output divider):?0: 0uA (Hi-Z) Engineering use only?1: 1uA. Engineering use only?2: 2uA. Use when Fout <= 67MHz?3: 3uA. Use when Fout > 67MHz?4-7: 4uA-7uA. Engineering use only"]
    #[inline(always)]
    pub fn icp_sel(&self) -> ICP_SEL_R {
        ICP_SEL_R::new(((self.bits >> 16) & 0x07) as u8)
    }
    #[doc = "Bits 20:21 - Selects the source of the system PLL1 clock."]
    #[inline(always)]
    pub fn bypass_sel(&self) -> BYPASS_SEL_R {
        BYPASS_SEL_R::new(((self.bits >> 20) & 0x03) as u8)
    }
    #[doc = "Bit 30 - Isolation control of PLL outputs. This also internally resets the PLL. De-assert >= 5us after ENABLE=1. Assertion can happen in same write as ENABLE=0. Do not change while PLL output is selected.?0: Isolate outputs; Precharge PLL control voltage if PLL0_TEST.FAST_LOCK_EN is set to 1.?1: Do not isolate outputs"]
    #[inline(always)]
    pub fn isolate_n(&self) -> ISOLATE_N_R {
        ISOLATE_N_R::new(((self.bits >> 30) & 0x01) != 0)
    }
    #[doc = "Bit 31 - Master enable for PLL power gate. Refer to ISOLATE_N field for required sequencing.?0: Block is powered off?1: Block is powered on"]
    #[inline(always)]
    pub fn enable(&self) -> ENABLE_R {
        ENABLE_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:7 - Control bits for feedback divider: Valid divide is 8-256. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn feedback_div(&mut self) -> FEEDBACK_DIV_W {
        FEEDBACK_DIV_W { w: self }
    }
    #[doc = "Bits 8:13 - Control bits for reference divider: Divide by 2=0001, ?, divide by 64=111111. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn reference_div(&mut self) -> REFERENCE_DIV_W {
        REFERENCE_DIV_W { w: self }
    }
    #[doc = "Bits 14:15 - Control bits for Output divider. Do not change while PLL output is selected."]
    #[inline(always)]
    pub fn output_div(&mut self) -> OUTPUT_DIV_W {
        OUTPUT_DIV_W { w: self }
    }
    #[doc = "Bits 16:18 - Programmable charge pump current between 0uA and 7uA. Do not change while the PLL output is selected. For functional operation, the value must be set according to the PLL output frequency Fout (measured before the output divider):?0: 0uA (Hi-Z) Engineering use only?1: 1uA. Engineering use only?2: 2uA. Use when Fout <= 67MHz?3: 3uA. Use when Fout > 67MHz?4-7: 4uA-7uA. Engineering use only"]
    #[inline(always)]
    pub fn icp_sel(&mut self) -> ICP_SEL_W {
        ICP_SEL_W { w: self }
    }
    #[doc = "Bits 20:21 - Selects the source of the system PLL1 clock."]
    #[inline(always)]
    pub fn bypass_sel(&mut self) -> BYPASS_SEL_W {
        BYPASS_SEL_W { w: self }
    }
    #[doc = "Bit 30 - Isolation control of PLL outputs. This also internally resets the PLL. De-assert >= 5us after ENABLE=1. Assertion can happen in same write as ENABLE=0. Do not change while PLL output is selected.?0: Isolate outputs; Precharge PLL control voltage if PLL0_TEST.FAST_LOCK_EN is set to 1.?1: Do not isolate outputs"]
    #[inline(always)]
    pub fn isolate_n(&mut self) -> ISOLATE_N_W {
        ISOLATE_N_W { w: self }
    }
    #[doc = "Bit 31 - Master enable for PLL power gate. Refer to ISOLATE_N field for required sequencing.?0: Block is powered off?1: Block is powered on"]
    #[inline(always)]
    pub fn enable(&mut self) -> ENABLE_W {
        ENABLE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "PLL #1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1_config](index.html) module"]
pub struct PLL1_CONFIG_SPEC;
impl crate::RegisterSpec for PLL1_CONFIG_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pll1_config::R](R) reader structure"]
impl crate::Readable for PLL1_CONFIG_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pll1_config::W](W) writer structure"]
impl crate::Writable for PLL1_CONFIG_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PLL1_CONFIG to value 0"]
impl crate::Resettable for PLL1_CONFIG_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
