#[doc = "Register `SYNC_CTL` reader"]
pub struct R(crate::R<SYNC_CTL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<SYNC_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<SYNC_CTL_SPEC>> for R {
    fn from(reader: crate::R<SYNC_CTL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `SYNC_CTL` writer"]
pub struct W(crate::W<SYNC_CTL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<SYNC_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<SYNC_CTL_SPEC>> for W {
    fn from(writer: crate::W<SYNC_CTL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `IO_SYNC_EN` reader - Synchronization of the IO pin input signals to \"clk_fabric\", one bit for each IO pin: IO_SYNC_EN\\[i\\]
is for IO pin i.?'0': No synchronization.?'1': Synchronization."]
pub struct IO_SYNC_EN_R(crate::FieldReader<u8, u8>);
impl IO_SYNC_EN_R {
    pub(crate) fn new(bits: u8) -> Self {
        IO_SYNC_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for IO_SYNC_EN_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `IO_SYNC_EN` writer - Synchronization of the IO pin input signals to \"clk_fabric\", one bit for each IO pin: IO_SYNC_EN\\[i\\]
is for IO pin i.?'0': No synchronization.?'1': Synchronization."]
pub struct IO_SYNC_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> IO_SYNC_EN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
}
#[doc = "Field `CHIP_SYNC_EN` reader - Synchronization of the chip input signals to \"clk_fabric\", one bit for each input: CHIP_SYNC_EN\\[i\\]
is for input i.?'0': No synchronization.?'1': Synchronization."]
pub struct CHIP_SYNC_EN_R(crate::FieldReader<u8, u8>);
impl CHIP_SYNC_EN_R {
    pub(crate) fn new(bits: u8) -> Self {
        CHIP_SYNC_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CHIP_SYNC_EN_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CHIP_SYNC_EN` writer - Synchronization of the chip input signals to \"clk_fabric\", one bit for each input: CHIP_SYNC_EN\\[i\\]
is for input i.?'0': No synchronization.?'1': Synchronization."]
pub struct CHIP_SYNC_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> CHIP_SYNC_EN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:7 - Synchronization of the IO pin input signals to \"clk_fabric\", one bit for each IO pin: IO_SYNC_EN\\[i\\]
is for IO pin i.?'0': No synchronization.?'1': Synchronization."]
    #[inline(always)]
    pub fn io_sync_en(&self) -> IO_SYNC_EN_R {
        IO_SYNC_EN_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bits 8:15 - Synchronization of the chip input signals to \"clk_fabric\", one bit for each input: CHIP_SYNC_EN\\[i\\]
is for input i.?'0': No synchronization.?'1': Synchronization."]
    #[inline(always)]
    pub fn chip_sync_en(&self) -> CHIP_SYNC_EN_R {
        CHIP_SYNC_EN_R::new(((self.bits >> 8) & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bits 0:7 - Synchronization of the IO pin input signals to \"clk_fabric\", one bit for each IO pin: IO_SYNC_EN\\[i\\]
is for IO pin i.?'0': No synchronization.?'1': Synchronization."]
    #[inline(always)]
    pub fn io_sync_en(&mut self) -> IO_SYNC_EN_W {
        IO_SYNC_EN_W { w: self }
    }
    #[doc = "Bits 8:15 - Synchronization of the chip input signals to \"clk_fabric\", one bit for each input: CHIP_SYNC_EN\\[i\\]
is for input i.?'0': No synchronization.?'1': Synchronization."]
    #[inline(always)]
    pub fn chip_sync_en(&mut self) -> CHIP_SYNC_EN_W {
        CHIP_SYNC_EN_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Synchronization control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sync_ctl](index.html) module"]
pub struct SYNC_CTL_SPEC;
impl crate::RegisterSpec for SYNC_CTL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [sync_ctl::R](R) reader structure"]
impl crate::Readable for SYNC_CTL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sync_ctl::W](W) writer structure"]
impl crate::Writable for SYNC_CTL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets SYNC_CTL to value 0"]
impl crate::Resettable for SYNC_CTL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
