#[doc = "Register `CLK_SELECT` reader"]
pub struct R(crate::R<CLK_SELECT_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CLK_SELECT_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CLK_SELECT_SPEC>> for R {
    fn from(reader: crate::R<CLK_SELECT_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CLK_SELECT` writer"]
pub struct W(crate::W<CLK_SELECT_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CLK_SELECT_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CLK_SELECT_SPEC>> for W {
    fn from(writer: crate::W<CLK_SELECT_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN\\[0\\].?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note that using DSI_OUT\\[3:0\\]
as HFCLK source will also result in undefined behavior. These values are available strictly to provide a clock in DSI_IN\\[0\\].\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DIRECT_SEL_A {
    #[doc = "0: No description available"]
    IMO = 0,
    #[doc = "1: No description available"]
    EXTCLK = 1,
    #[doc = "2: No description available"]
    ECO = 2,
    #[doc = "4: No description available"]
    DSI0 = 4,
    #[doc = "5: No description available"]
    DSI1 = 5,
    #[doc = "6: No description available"]
    DSI2 = 6,
    #[doc = "7: No description available"]
    DSI3 = 7,
}
impl From<DIRECT_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: DIRECT_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `DIRECT_SEL` reader - Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN\\[0\\].?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note that using DSI_OUT\\[3:0\\]
as HFCLK source will also result in undefined behavior. These values are available strictly to provide a clock in DSI_IN\\[0\\]."]
pub struct DIRECT_SEL_R(crate::FieldReader<u8, DIRECT_SEL_A>);
impl DIRECT_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        DIRECT_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<DIRECT_SEL_A> {
        match self.bits {
            0 => Some(DIRECT_SEL_A::IMO),
            1 => Some(DIRECT_SEL_A::EXTCLK),
            2 => Some(DIRECT_SEL_A::ECO),
            4 => Some(DIRECT_SEL_A::DSI0),
            5 => Some(DIRECT_SEL_A::DSI1),
            6 => Some(DIRECT_SEL_A::DSI2),
            7 => Some(DIRECT_SEL_A::DSI3),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `IMO`"]
    #[inline(always)]
    pub fn is_imo(&self) -> bool {
        **self == DIRECT_SEL_A::IMO
    }
    #[doc = "Checks if the value of the field is `EXTCLK`"]
    #[inline(always)]
    pub fn is_extclk(&self) -> bool {
        **self == DIRECT_SEL_A::EXTCLK
    }
    #[doc = "Checks if the value of the field is `ECO`"]
    #[inline(always)]
    pub fn is_eco(&self) -> bool {
        **self == DIRECT_SEL_A::ECO
    }
    #[doc = "Checks if the value of the field is `DSI0`"]
    #[inline(always)]
    pub fn is_dsi0(&self) -> bool {
        **self == DIRECT_SEL_A::DSI0
    }
    #[doc = "Checks if the value of the field is `DSI1`"]
    #[inline(always)]
    pub fn is_dsi1(&self) -> bool {
        **self == DIRECT_SEL_A::DSI1
    }
    #[doc = "Checks if the value of the field is `DSI2`"]
    #[inline(always)]
    pub fn is_dsi2(&self) -> bool {
        **self == DIRECT_SEL_A::DSI2
    }
    #[doc = "Checks if the value of the field is `DSI3`"]
    #[inline(always)]
    pub fn is_dsi3(&self) -> bool {
        **self == DIRECT_SEL_A::DSI3
    }
}
impl core::ops::Deref for DIRECT_SEL_R {
    type Target = crate::FieldReader<u8, DIRECT_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DIRECT_SEL` writer - Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN\\[0\\].?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note that using DSI_OUT\\[3:0\\]
as HFCLK source will also result in undefined behavior. These values are available strictly to provide a clock in DSI_IN\\[0\\]."]
pub struct DIRECT_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> DIRECT_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DIRECT_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn imo(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::IMO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn extclk(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::EXTCLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn eco(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::ECO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi0(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::DSI0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi1(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::DSI1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi2(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::DSI2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi3(self) -> &'a mut W {
        self.variant(DIRECT_SEL_A::DSI3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
        self.w
    }
}
#[doc = "Selects a source the input of EXCO PLL1, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called DBL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DBL_SEL_A {
    #[doc = "0: No description available"]
    IMO = 0,
    #[doc = "1: No description available"]
    EXTCLK = 1,
    #[doc = "2: No description available"]
    ECO = 2,
    #[doc = "4: No description available"]
    DSI0 = 4,
    #[doc = "5: No description available"]
    DSI1 = 5,
    #[doc = "6: No description available"]
    DSI2 = 6,
    #[doc = "7: No description available"]
    DSI3 = 7,
}
impl From<DBL_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: DBL_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `DBL_SEL` reader - Selects a source the input of EXCO PLL1, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called DBL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
pub struct DBL_SEL_R(crate::FieldReader<u8, DBL_SEL_A>);
impl DBL_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        DBL_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<DBL_SEL_A> {
        match self.bits {
            0 => Some(DBL_SEL_A::IMO),
            1 => Some(DBL_SEL_A::EXTCLK),
            2 => Some(DBL_SEL_A::ECO),
            4 => Some(DBL_SEL_A::DSI0),
            5 => Some(DBL_SEL_A::DSI1),
            6 => Some(DBL_SEL_A::DSI2),
            7 => Some(DBL_SEL_A::DSI3),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `IMO`"]
    #[inline(always)]
    pub fn is_imo(&self) -> bool {
        **self == DBL_SEL_A::IMO
    }
    #[doc = "Checks if the value of the field is `EXTCLK`"]
    #[inline(always)]
    pub fn is_extclk(&self) -> bool {
        **self == DBL_SEL_A::EXTCLK
    }
    #[doc = "Checks if the value of the field is `ECO`"]
    #[inline(always)]
    pub fn is_eco(&self) -> bool {
        **self == DBL_SEL_A::ECO
    }
    #[doc = "Checks if the value of the field is `DSI0`"]
    #[inline(always)]
    pub fn is_dsi0(&self) -> bool {
        **self == DBL_SEL_A::DSI0
    }
    #[doc = "Checks if the value of the field is `DSI1`"]
    #[inline(always)]
    pub fn is_dsi1(&self) -> bool {
        **self == DBL_SEL_A::DSI1
    }
    #[doc = "Checks if the value of the field is `DSI2`"]
    #[inline(always)]
    pub fn is_dsi2(&self) -> bool {
        **self == DBL_SEL_A::DSI2
    }
    #[doc = "Checks if the value of the field is `DSI3`"]
    #[inline(always)]
    pub fn is_dsi3(&self) -> bool {
        **self == DBL_SEL_A::DSI3
    }
}
impl core::ops::Deref for DBL_SEL_R {
    type Target = crate::FieldReader<u8, DBL_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DBL_SEL` writer - Selects a source the input of EXCO PLL1, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called DBL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
pub struct DBL_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> DBL_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DBL_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn imo(self) -> &'a mut W {
        self.variant(DBL_SEL_A::IMO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn extclk(self) -> &'a mut W {
        self.variant(DBL_SEL_A::EXTCLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn eco(self) -> &'a mut W {
        self.variant(DBL_SEL_A::ECO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi0(self) -> &'a mut W {
        self.variant(DBL_SEL_A::DSI0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi1(self) -> &'a mut W {
        self.variant(DBL_SEL_A::DSI1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi2(self) -> &'a mut W {
        self.variant(DBL_SEL_A::DSI2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi3(self) -> &'a mut W {
        self.variant(DBL_SEL_A::DSI3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
        self.w
    }
}
#[doc = "Selects a source the input of EXCO PLL0, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called PLL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum PLL_SEL_A {
    #[doc = "0: No description available"]
    IMO = 0,
    #[doc = "1: No description available"]
    EXTCLK = 1,
    #[doc = "2: No description available"]
    ECO = 2,
    #[doc = "3: No description available"]
    DPLL = 3,
    #[doc = "4: No description available"]
    DSI0 = 4,
    #[doc = "5: No description available"]
    DSI1 = 5,
    #[doc = "6: No description available"]
    DSI2 = 6,
    #[doc = "7: No description available"]
    DSI3 = 7,
}
impl From<PLL_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: PLL_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `PLL_SEL` reader - Selects a source the input of EXCO PLL0, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called PLL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
pub struct PLL_SEL_R(crate::FieldReader<u8, PLL_SEL_A>);
impl PLL_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        PLL_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> PLL_SEL_A {
        match self.bits {
            0 => PLL_SEL_A::IMO,
            1 => PLL_SEL_A::EXTCLK,
            2 => PLL_SEL_A::ECO,
            3 => PLL_SEL_A::DPLL,
            4 => PLL_SEL_A::DSI0,
            5 => PLL_SEL_A::DSI1,
            6 => PLL_SEL_A::DSI2,
            7 => PLL_SEL_A::DSI3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `IMO`"]
    #[inline(always)]
    pub fn is_imo(&self) -> bool {
        **self == PLL_SEL_A::IMO
    }
    #[doc = "Checks if the value of the field is `EXTCLK`"]
    #[inline(always)]
    pub fn is_extclk(&self) -> bool {
        **self == PLL_SEL_A::EXTCLK
    }
    #[doc = "Checks if the value of the field is `ECO`"]
    #[inline(always)]
    pub fn is_eco(&self) -> bool {
        **self == PLL_SEL_A::ECO
    }
    #[doc = "Checks if the value of the field is `DPLL`"]
    #[inline(always)]
    pub fn is_dpll(&self) -> bool {
        **self == PLL_SEL_A::DPLL
    }
    #[doc = "Checks if the value of the field is `DSI0`"]
    #[inline(always)]
    pub fn is_dsi0(&self) -> bool {
        **self == PLL_SEL_A::DSI0
    }
    #[doc = "Checks if the value of the field is `DSI1`"]
    #[inline(always)]
    pub fn is_dsi1(&self) -> bool {
        **self == PLL_SEL_A::DSI1
    }
    #[doc = "Checks if the value of the field is `DSI2`"]
    #[inline(always)]
    pub fn is_dsi2(&self) -> bool {
        **self == PLL_SEL_A::DSI2
    }
    #[doc = "Checks if the value of the field is `DSI3`"]
    #[inline(always)]
    pub fn is_dsi3(&self) -> bool {
        **self == PLL_SEL_A::DSI3
    }
}
impl core::ops::Deref for PLL_SEL_R {
    type Target = crate::FieldReader<u8, PLL_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PLL_SEL` writer - Selects a source the input of EXCO PLL0, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called PLL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
pub struct PLL_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> PLL_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLL_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn imo(self) -> &'a mut W {
        self.variant(PLL_SEL_A::IMO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn extclk(self) -> &'a mut W {
        self.variant(PLL_SEL_A::EXTCLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn eco(self) -> &'a mut W {
        self.variant(PLL_SEL_A::ECO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dpll(self) -> &'a mut W {
        self.variant(PLL_SEL_A::DPLL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi0(self) -> &'a mut W {
        self.variant(PLL_SEL_A::DSI0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi1(self) -> &'a mut W {
        self.variant(PLL_SEL_A::DSI1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi2(self) -> &'a mut W {
        self.variant(PLL_SEL_A::DSI2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi3(self) -> &'a mut W {
        self.variant(PLL_SEL_A::DSI3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 6)) | ((value as u32 & 0x07) << 6);
        self.w
    }
}
#[doc = "Selects a source for the input of DPLL.?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DPLLIN_SEL_A {
    #[doc = "0: No description available"]
    IMO = 0,
    #[doc = "1: No description available"]
    EXTCLK = 1,
    #[doc = "2: No description available"]
    ECO = 2,
    #[doc = "4: No description available"]
    DSI0 = 4,
    #[doc = "5: No description available"]
    DSI1 = 5,
    #[doc = "6: No description available"]
    DSI2 = 6,
    #[doc = "7: No description available"]
    DSI3 = 7,
}
impl From<DPLLIN_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: DPLLIN_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `DPLLIN_SEL` reader - Selects a source for the input of DPLL.?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
pub struct DPLLIN_SEL_R(crate::FieldReader<u8, DPLLIN_SEL_A>);
impl DPLLIN_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        DPLLIN_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<DPLLIN_SEL_A> {
        match self.bits {
            0 => Some(DPLLIN_SEL_A::IMO),
            1 => Some(DPLLIN_SEL_A::EXTCLK),
            2 => Some(DPLLIN_SEL_A::ECO),
            4 => Some(DPLLIN_SEL_A::DSI0),
            5 => Some(DPLLIN_SEL_A::DSI1),
            6 => Some(DPLLIN_SEL_A::DSI2),
            7 => Some(DPLLIN_SEL_A::DSI3),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `IMO`"]
    #[inline(always)]
    pub fn is_imo(&self) -> bool {
        **self == DPLLIN_SEL_A::IMO
    }
    #[doc = "Checks if the value of the field is `EXTCLK`"]
    #[inline(always)]
    pub fn is_extclk(&self) -> bool {
        **self == DPLLIN_SEL_A::EXTCLK
    }
    #[doc = "Checks if the value of the field is `ECO`"]
    #[inline(always)]
    pub fn is_eco(&self) -> bool {
        **self == DPLLIN_SEL_A::ECO
    }
    #[doc = "Checks if the value of the field is `DSI0`"]
    #[inline(always)]
    pub fn is_dsi0(&self) -> bool {
        **self == DPLLIN_SEL_A::DSI0
    }
    #[doc = "Checks if the value of the field is `DSI1`"]
    #[inline(always)]
    pub fn is_dsi1(&self) -> bool {
        **self == DPLLIN_SEL_A::DSI1
    }
    #[doc = "Checks if the value of the field is `DSI2`"]
    #[inline(always)]
    pub fn is_dsi2(&self) -> bool {
        **self == DPLLIN_SEL_A::DSI2
    }
    #[doc = "Checks if the value of the field is `DSI3`"]
    #[inline(always)]
    pub fn is_dsi3(&self) -> bool {
        **self == DPLLIN_SEL_A::DSI3
    }
}
impl core::ops::Deref for DPLLIN_SEL_R {
    type Target = crate::FieldReader<u8, DPLLIN_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DPLLIN_SEL` writer - Selects a source for the input of DPLL.?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
pub struct DPLLIN_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> DPLLIN_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DPLLIN_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn imo(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::IMO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn extclk(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::EXTCLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn eco(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::ECO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi0(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::DSI0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi1(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::DSI1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi2(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::DSI2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi3(self) -> &'a mut W {
        self.variant(DPLLIN_SEL_A::DSI3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 9)) | ((value as u32 & 0x07) << 9);
        self.w
    }
}
#[doc = "Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT\\[0\\]?1: DSI_OUT\\[1\\]?2: DSI_OUT\\[2\\]?3: DSI_OUT\\[3\\]\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DPLLREF_SEL_A {
    #[doc = "0: No description available"]
    DSI0 = 0,
    #[doc = "1: No description available"]
    DSI1 = 1,
    #[doc = "2: No description available"]
    DSI2 = 2,
    #[doc = "3: No description available"]
    DSI3 = 3,
}
impl From<DPLLREF_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: DPLLREF_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `DPLLREF_SEL` reader - Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT\\[0\\]?1: DSI_OUT\\[1\\]?2: DSI_OUT\\[2\\]?3: DSI_OUT\\[3\\]"]
pub struct DPLLREF_SEL_R(crate::FieldReader<u8, DPLLREF_SEL_A>);
impl DPLLREF_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        DPLLREF_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> DPLLREF_SEL_A {
        match self.bits {
            0 => DPLLREF_SEL_A::DSI0,
            1 => DPLLREF_SEL_A::DSI1,
            2 => DPLLREF_SEL_A::DSI2,
            3 => DPLLREF_SEL_A::DSI3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `DSI0`"]
    #[inline(always)]
    pub fn is_dsi0(&self) -> bool {
        **self == DPLLREF_SEL_A::DSI0
    }
    #[doc = "Checks if the value of the field is `DSI1`"]
    #[inline(always)]
    pub fn is_dsi1(&self) -> bool {
        **self == DPLLREF_SEL_A::DSI1
    }
    #[doc = "Checks if the value of the field is `DSI2`"]
    #[inline(always)]
    pub fn is_dsi2(&self) -> bool {
        **self == DPLLREF_SEL_A::DSI2
    }
    #[doc = "Checks if the value of the field is `DSI3`"]
    #[inline(always)]
    pub fn is_dsi3(&self) -> bool {
        **self == DPLLREF_SEL_A::DSI3
    }
}
impl core::ops::Deref for DPLLREF_SEL_R {
    type Target = crate::FieldReader<u8, DPLLREF_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DPLLREF_SEL` writer - Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT\\[0\\]?1: DSI_OUT\\[1\\]?2: DSI_OUT\\[2\\]?3: DSI_OUT\\[3\\]"]
pub struct DPLLREF_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> DPLLREF_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DPLLREF_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi0(self) -> &'a mut W {
        self.variant(DPLLREF_SEL_A::DSI0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi1(self) -> &'a mut W {
        self.variant(DPLLREF_SEL_A::DSI1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi2(self) -> &'a mut W {
        self.variant(DPLLREF_SEL_A::DSI2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi3(self) -> &'a mut W {
        self.variant(DPLLREF_SEL_A::DSI3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
        self.w
    }
}
#[doc = "Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0. Requires at least two different writes to unlock.?Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all WATCHDOG registers at the same time.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum WDT_LOCK_A {
    #[doc = "0: No description available"]
    NO_CHG = 0,
    #[doc = "1: No description available"]
    CLR0 = 1,
    #[doc = "2: No description available"]
    CLR1 = 2,
    #[doc = "3: No description available"]
    SET01 = 3,
}
impl From<WDT_LOCK_A> for u8 {
    #[inline(always)]
    fn from(variant: WDT_LOCK_A) -> Self {
        variant as _
    }
}
#[doc = "Field `WDT_LOCK` reader - Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0. Requires at least two different writes to unlock.?Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all WATCHDOG registers at the same time."]
pub struct WDT_LOCK_R(crate::FieldReader<u8, WDT_LOCK_A>);
impl WDT_LOCK_R {
    pub(crate) fn new(bits: u8) -> Self {
        WDT_LOCK_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> WDT_LOCK_A {
        match self.bits {
            0 => WDT_LOCK_A::NO_CHG,
            1 => WDT_LOCK_A::CLR0,
            2 => WDT_LOCK_A::CLR1,
            3 => WDT_LOCK_A::SET01,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `NO_CHG`"]
    #[inline(always)]
    pub fn is_no_chg(&self) -> bool {
        **self == WDT_LOCK_A::NO_CHG
    }
    #[doc = "Checks if the value of the field is `CLR0`"]
    #[inline(always)]
    pub fn is_clr0(&self) -> bool {
        **self == WDT_LOCK_A::CLR0
    }
    #[doc = "Checks if the value of the field is `CLR1`"]
    #[inline(always)]
    pub fn is_clr1(&self) -> bool {
        **self == WDT_LOCK_A::CLR1
    }
    #[doc = "Checks if the value of the field is `SET01`"]
    #[inline(always)]
    pub fn is_set01(&self) -> bool {
        **self == WDT_LOCK_A::SET01
    }
}
impl core::ops::Deref for WDT_LOCK_R {
    type Target = crate::FieldReader<u8, WDT_LOCK_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `WDT_LOCK` writer - Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0. Requires at least two different writes to unlock.?Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all WATCHDOG registers at the same time."]
pub struct WDT_LOCK_W<'a> {
    w: &'a mut W,
}
impl<'a> WDT_LOCK_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: WDT_LOCK_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn no_chg(self) -> &'a mut W {
        self.variant(WDT_LOCK_A::NO_CHG)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn clr0(self) -> &'a mut W {
        self.variant(WDT_LOCK_A::CLR0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn clr1(self) -> &'a mut W {
        self.variant(WDT_LOCK_A::CLR1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn set01(self) -> &'a mut W {
        self.variant(WDT_LOCK_A::SET01)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14);
        self.w
    }
}
#[doc = "Selects the source for HFCLK.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum HFCLK_SEL_A {
    #[doc = "0: No description available"]
    DIRECT_SEL = 0,
    #[doc = "1: No description available"]
    DBL = 1,
    #[doc = "2: No description available"]
    PLL = 2,
}
impl From<HFCLK_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: HFCLK_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `HFCLK_SEL` reader - Selects the source for HFCLK."]
pub struct HFCLK_SEL_R(crate::FieldReader<u8, HFCLK_SEL_A>);
impl HFCLK_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        HFCLK_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<HFCLK_SEL_A> {
        match self.bits {
            0 => Some(HFCLK_SEL_A::DIRECT_SEL),
            1 => Some(HFCLK_SEL_A::DBL),
            2 => Some(HFCLK_SEL_A::PLL),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `DIRECT_SEL`"]
    #[inline(always)]
    pub fn is_direct_sel(&self) -> bool {
        **self == HFCLK_SEL_A::DIRECT_SEL
    }
    #[doc = "Checks if the value of the field is `DBL`"]
    #[inline(always)]
    pub fn is_dbl(&self) -> bool {
        **self == HFCLK_SEL_A::DBL
    }
    #[doc = "Checks if the value of the field is `PLL`"]
    #[inline(always)]
    pub fn is_pll(&self) -> bool {
        **self == HFCLK_SEL_A::PLL
    }
}
impl core::ops::Deref for HFCLK_SEL_R {
    type Target = crate::FieldReader<u8, HFCLK_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HFCLK_SEL` writer - Selects the source for HFCLK."]
pub struct HFCLK_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> HFCLK_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: HFCLK_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn direct_sel(self) -> &'a mut W {
        self.variant(HFCLK_SEL_A::DIRECT_SEL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dbl(self) -> &'a mut W {
        self.variant(HFCLK_SEL_A::DBL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pll(self) -> &'a mut W {
        self.variant(HFCLK_SEL_A::PLL)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
        self.w
    }
}
#[doc = "Field `HALF_EN` reader - This bit impact products using CPUSSv1 only. It has no effect on products using CPUSSv2.?FLASH Wait-state selection. This must be set to 1 when clk_sys is set to a frequency greater than 24MHz.?0: Access FLASH using 0 wait-states. Only use this setting when HFCLK is <=24MHz.?1: Access FLASH using 1 wait-state. Safe to use this setting for any clock frequency."]
pub struct HALF_EN_R(crate::FieldReader<bool, bool>);
impl HALF_EN_R {
    pub(crate) fn new(bits: bool) -> Self {
        HALF_EN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HALF_EN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HALF_EN` writer - This bit impact products using CPUSSv1 only. It has no effect on products using CPUSSv2.?FLASH Wait-state selection. This must be set to 1 when clk_sys is set to a frequency greater than 24MHz.?0: Access FLASH using 0 wait-states. Only use this setting when HFCLK is <=24MHz.?1: Access FLASH using 1 wait-state. Safe to use this setting for any clock frequency."]
pub struct HALF_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> HALF_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
        self.w
    }
}
#[doc = "SYSCLK Pre-Scaler Value.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum SYSCLK_DIV_A {
    #[doc = "0: No description available"]
    NO_DIV = 0,
    #[doc = "1: No description available"]
    DIV_BY_2 = 1,
    #[doc = "2: No description available"]
    DIV_BY_4 = 2,
    #[doc = "3: No description available"]
    DIV_BY_8 = 3,
    #[doc = "4: No description available"]
    DIV_BY_16 = 4,
    #[doc = "5: No description available"]
    DIV_BY_32 = 5,
    #[doc = "6: No description available"]
    DIV_BY_64 = 6,
    #[doc = "7: No description available"]
    DIV_BY_128 = 7,
}
impl From<SYSCLK_DIV_A> for u8 {
    #[inline(always)]
    fn from(variant: SYSCLK_DIV_A) -> Self {
        variant as _
    }
}
#[doc = "Field `SYSCLK_DIV` reader - SYSCLK Pre-Scaler Value."]
pub struct SYSCLK_DIV_R(crate::FieldReader<u8, SYSCLK_DIV_A>);
impl SYSCLK_DIV_R {
    pub(crate) fn new(bits: u8) -> Self {
        SYSCLK_DIV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SYSCLK_DIV_A {
        match self.bits {
            0 => SYSCLK_DIV_A::NO_DIV,
            1 => SYSCLK_DIV_A::DIV_BY_2,
            2 => SYSCLK_DIV_A::DIV_BY_4,
            3 => SYSCLK_DIV_A::DIV_BY_8,
            4 => SYSCLK_DIV_A::DIV_BY_16,
            5 => SYSCLK_DIV_A::DIV_BY_32,
            6 => SYSCLK_DIV_A::DIV_BY_64,
            7 => SYSCLK_DIV_A::DIV_BY_128,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `NO_DIV`"]
    #[inline(always)]
    pub fn is_no_div(&self) -> bool {
        **self == SYSCLK_DIV_A::NO_DIV
    }
    #[doc = "Checks if the value of the field is `DIV_BY_2`"]
    #[inline(always)]
    pub fn is_div_by_2(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_2
    }
    #[doc = "Checks if the value of the field is `DIV_BY_4`"]
    #[inline(always)]
    pub fn is_div_by_4(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_4
    }
    #[doc = "Checks if the value of the field is `DIV_BY_8`"]
    #[inline(always)]
    pub fn is_div_by_8(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_8
    }
    #[doc = "Checks if the value of the field is `DIV_BY_16`"]
    #[inline(always)]
    pub fn is_div_by_16(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_16
    }
    #[doc = "Checks if the value of the field is `DIV_BY_32`"]
    #[inline(always)]
    pub fn is_div_by_32(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_32
    }
    #[doc = "Checks if the value of the field is `DIV_BY_64`"]
    #[inline(always)]
    pub fn is_div_by_64(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_64
    }
    #[doc = "Checks if the value of the field is `DIV_BY_128`"]
    #[inline(always)]
    pub fn is_div_by_128(&self) -> bool {
        **self == SYSCLK_DIV_A::DIV_BY_128
    }
}
impl core::ops::Deref for SYSCLK_DIV_R {
    type Target = crate::FieldReader<u8, SYSCLK_DIV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SYSCLK_DIV` writer - SYSCLK Pre-Scaler Value."]
pub struct SYSCLK_DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> SYSCLK_DIV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SYSCLK_DIV_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn no_div(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::NO_DIV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_2(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_4(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_4)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_8(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_8)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_16(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_16)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_32(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_32)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_64(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_64)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn div_by_128(self) -> &'a mut W {
        self.variant(SYSCLK_DIV_A::DIV_BY_128)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:2 - Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN\\[0\\].?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note that using DSI_OUT\\[3:0\\]
as HFCLK source will also result in undefined behavior. These values are available strictly to provide a clock in DSI_IN\\[0\\]."]
    #[inline(always)]
    pub fn direct_sel(&self) -> DIRECT_SEL_R {
        DIRECT_SEL_R::new((self.bits & 0x07) as u8)
    }
    #[doc = "Bits 3:5 - Selects a source the input of EXCO PLL1, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called DBL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
    #[inline(always)]
    pub fn dbl_sel(&self) -> DBL_SEL_R {
        DBL_SEL_R::new(((self.bits >> 3) & 0x07) as u8)
    }
    #[doc = "Bits 6:8 - Selects a source the input of EXCO PLL0, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called PLL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
    #[inline(always)]
    pub fn pll_sel(&self) -> PLL_SEL_R {
        PLL_SEL_R::new(((self.bits >> 6) & 0x07) as u8)
    }
    #[doc = "Bits 9:11 - Selects a source for the input of DPLL.?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
    #[inline(always)]
    pub fn dpllin_sel(&self) -> DPLLIN_SEL_R {
        DPLLIN_SEL_R::new(((self.bits >> 9) & 0x07) as u8)
    }
    #[doc = "Bits 12:13 - Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT\\[0\\]?1: DSI_OUT\\[1\\]?2: DSI_OUT\\[2\\]?3: DSI_OUT\\[3\\]"]
    #[inline(always)]
    pub fn dpllref_sel(&self) -> DPLLREF_SEL_R {
        DPLLREF_SEL_R::new(((self.bits >> 12) & 0x03) as u8)
    }
    #[doc = "Bits 14:15 - Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0. Requires at least two different writes to unlock.?Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all WATCHDOG registers at the same time."]
    #[inline(always)]
    pub fn wdt_lock(&self) -> WDT_LOCK_R {
        WDT_LOCK_R::new(((self.bits >> 14) & 0x03) as u8)
    }
    #[doc = "Bits 16:17 - Selects the source for HFCLK."]
    #[inline(always)]
    pub fn hfclk_sel(&self) -> HFCLK_SEL_R {
        HFCLK_SEL_R::new(((self.bits >> 16) & 0x03) as u8)
    }
    #[doc = "Bit 18 - This bit impact products using CPUSSv1 only. It has no effect on products using CPUSSv2.?FLASH Wait-state selection. This must be set to 1 when clk_sys is set to a frequency greater than 24MHz.?0: Access FLASH using 0 wait-states. Only use this setting when HFCLK is <=24MHz.?1: Access FLASH using 1 wait-state. Safe to use this setting for any clock frequency."]
    #[inline(always)]
    pub fn half_en(&self) -> HALF_EN_R {
        HALF_EN_R::new(((self.bits >> 18) & 0x01) != 0)
    }
    #[doc = "Bits 19:21 - SYSCLK Pre-Scaler Value."]
    #[inline(always)]
    pub fn sysclk_div(&self) -> SYSCLK_DIV_R {
        SYSCLK_DIV_R::new(((self.bits >> 19) & 0x07) as u8)
    }
}
impl W {
    #[doc = "Bits 0:2 - Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN\\[0\\].?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note that using DSI_OUT\\[3:0\\]
as HFCLK source will also result in undefined behavior. These values are available strictly to provide a clock in DSI_IN\\[0\\]."]
    #[inline(always)]
    pub fn direct_sel(&mut self) -> DIRECT_SEL_W {
        DIRECT_SEL_W { w: self }
    }
    #[doc = "Bits 3:5 - Selects a source the input of EXCO PLL1, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called DBL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
    #[inline(always)]
    pub fn dbl_sel(&mut self) -> DBL_SEL_W {
        DBL_SEL_W { w: self }
    }
    #[doc = "Bits 6:8 - Selects a source the input of EXCO PLL0, if supported. ?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.?Note: this is called PLL_SEL for legacy reasons, and cannot be changed without breaking collateral for multiple existing products."]
    #[inline(always)]
    pub fn pll_sel(&mut self) -> PLL_SEL_W {
        PLL_SEL_W { w: self }
    }
    #[doc = "Bits 9:11 - Selects a source for the input of DPLL.?Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior."]
    #[inline(always)]
    pub fn dpllin_sel(&mut self) -> DPLLIN_SEL_W {
        DPLLIN_SEL_W { w: self }
    }
    #[doc = "Bits 12:13 - Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT\\[0\\]?1: DSI_OUT\\[1\\]?2: DSI_OUT\\[2\\]?3: DSI_OUT\\[3\\]"]
    #[inline(always)]
    pub fn dpllref_sel(&mut self) -> DPLLREF_SEL_W {
        DPLLREF_SEL_W { w: self }
    }
    #[doc = "Bits 14:15 - Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0. Requires at least two different writes to unlock.?Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all WATCHDOG registers at the same time."]
    #[inline(always)]
    pub fn wdt_lock(&mut self) -> WDT_LOCK_W {
        WDT_LOCK_W { w: self }
    }
    #[doc = "Bits 16:17 - Selects the source for HFCLK."]
    #[inline(always)]
    pub fn hfclk_sel(&mut self) -> HFCLK_SEL_W {
        HFCLK_SEL_W { w: self }
    }
    #[doc = "Bit 18 - This bit impact products using CPUSSv1 only. It has no effect on products using CPUSSv2.?FLASH Wait-state selection. This must be set to 1 when clk_sys is set to a frequency greater than 24MHz.?0: Access FLASH using 0 wait-states. Only use this setting when HFCLK is <=24MHz.?1: Access FLASH using 1 wait-state. Safe to use this setting for any clock frequency."]
    #[inline(always)]
    pub fn half_en(&mut self) -> HALF_EN_W {
        HALF_EN_W { w: self }
    }
    #[doc = "Bits 19:21 - SYSCLK Pre-Scaler Value."]
    #[inline(always)]
    pub fn sysclk_div(&mut self) -> SYSCLK_DIV_W {
        SYSCLK_DIV_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Clock Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_select](index.html) module"]
pub struct CLK_SELECT_SPEC;
impl crate::RegisterSpec for CLK_SELECT_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [clk_select::R](R) reader structure"]
impl crate::Readable for CLK_SELECT_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [clk_select::W](W) writer structure"]
impl crate::Writable for CLK_SELECT_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CLK_SELECT to value 0"]
impl crate::Resettable for CLK_SELECT_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
