#[doc = "Register `DPSLP_KEY_DELAY` reader"]
pub struct R(crate::R<DPSLP_KEY_DELAY_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DPSLP_KEY_DELAY_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<DPSLP_KEY_DELAY_SPEC>> for R {
    fn from(reader: crate::R<DPSLP_KEY_DELAY_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DPSLP_KEY_DELAY` writer"]
pub struct W(crate::W<DPSLP_KEY_DELAY_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DPSLP_KEY_DELAY_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<DPSLP_KEY_DELAY_SPEC>> for W {
    fn from(writer: crate::W<DPSLP_KEY_DELAY_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `WAKEUP_HOLDOFF` reader - Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep. PBOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded."]
pub struct WAKEUP_HOLDOFF_R(crate::FieldReader<u16, u16>);
impl WAKEUP_HOLDOFF_R {
    pub(crate) fn new(bits: u16) -> Self {
        WAKEUP_HOLDOFF_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for WAKEUP_HOLDOFF_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `WAKEUP_HOLDOFF` writer - Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep. PBOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded."]
pub struct WAKEUP_HOLDOFF_W<'a> {
    w: &'a mut W,
}
impl<'a> WAKEUP_HOLDOFF_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03ff) | (value as u16 & 0x03ff);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:9 - Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep. PBOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded."]
    #[inline(always)]
    pub fn wakeup_holdoff(&self) -> WAKEUP_HOLDOFF_R {
        WAKEUP_HOLDOFF_R::new((self.bits & 0x03ff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:9 - Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep. PBOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded."]
    #[inline(always)]
    pub fn wakeup_holdoff(&mut self) -> WAKEUP_HOLDOFF_W {
        WAKEUP_HOLDOFF_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "DeepSleep wakeup value for PWR_KEY_DELAY\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpslp_key_delay](index.html) module"]
pub struct DPSLP_KEY_DELAY_SPEC;
impl crate::RegisterSpec for DPSLP_KEY_DELAY_SPEC {
    type Ux = u16;
}
#[doc = "`read()` method returns [dpslp_key_delay::R](R) reader structure"]
impl crate::Readable for DPSLP_KEY_DELAY_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dpslp_key_delay::W](W) writer structure"]
impl crate::Writable for DPSLP_KEY_DELAY_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets DPSLP_KEY_DELAY to value 0"]
impl crate::Resettable for DPSLP_KEY_DELAY_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
