#[doc = "Register `CH_CTL29` reader"]
pub struct R(crate::R<CH_CTL29_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CH_CTL29_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CH_CTL29_SPEC>> for R {
    fn from(reader: crate::R<CH_CTL29_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CH_CTL29` writer"]
pub struct W(crate::W<CH_CTL29_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CH_CTL29_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CH_CTL29_SPEC>> for W {
    fn from(writer: crate::W<CH_CTL29_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PRIO` reader - Channel priority, with ?0? representing the highest priority and ?3? representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel."]
pub struct PRIO_R(crate::FieldReader<u8, u8>);
impl PRIO_R {
    pub(crate) fn new(bits: u8) -> Self {
        PRIO_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PRIO_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PRIO` writer - Channel priority, with ?0? representing the highest priority and ?3? representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel."]
pub struct PRIO_W<'a> {
    w: &'a mut W,
}
impl<'a> PRIO_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28);
        self.w
    }
}
#[doc = "Field `PING_PONG` reader - Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller.??Software sets this field to the desired descriptor structure.??Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to ?1?.?Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller."]
pub struct PING_PONG_R(crate::FieldReader<bool, bool>);
impl PING_PONG_R {
    pub(crate) fn new(bits: bool) -> Self {
        PING_PONG_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PING_PONG_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PING_PONG` writer - Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller.??Software sets this field to the desired descriptor structure.??Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to ?1?.?Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller."]
pub struct PING_PONG_W<'a> {
    w: &'a mut W,
}
impl<'a> PING_PONG_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
        self.w
    }
}
#[doc = "Field `ENABLED` reader - ?0?: channel disabled. The channel?s trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. ??1?: channel enabled.??Software sets this field to ?1? to enable a specific channel.??Hardware sets this field to ?0? on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel?s descriptor structure)."]
pub struct ENABLED_R(crate::FieldReader<bool, bool>);
impl ENABLED_R {
    pub(crate) fn new(bits: bool) -> Self {
        ENABLED_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ENABLED_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ENABLED` writer - ?0?: channel disabled. The channel?s trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. ??1?: channel enabled.??Software sets this field to ?1? to enable a specific channel.??Hardware sets this field to ?0? on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel?s descriptor structure)."]
pub struct ENABLED_W<'a> {
    w: &'a mut W,
}
impl<'a> ENABLED_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bits 28:29 - Channel priority, with ?0? representing the highest priority and ?3? representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel."]
    #[inline(always)]
    pub fn prio(&self) -> PRIO_R {
        PRIO_R::new(((self.bits >> 28) & 0x03) as u8)
    }
    #[doc = "Bit 30 - Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller.??Software sets this field to the desired descriptor structure.??Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to ?1?.?Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller."]
    #[inline(always)]
    pub fn ping_pong(&self) -> PING_PONG_R {
        PING_PONG_R::new(((self.bits >> 30) & 0x01) != 0)
    }
    #[doc = "Bit 31 - ?0?: channel disabled. The channel?s trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. ??1?: channel enabled.??Software sets this field to ?1? to enable a specific channel.??Hardware sets this field to ?0? on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel?s descriptor structure)."]
    #[inline(always)]
    pub fn enabled(&self) -> ENABLED_R {
        ENABLED_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 28:29 - Channel priority, with ?0? representing the highest priority and ?3? representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel."]
    #[inline(always)]
    pub fn prio(&mut self) -> PRIO_W {
        PRIO_W { w: self }
    }
    #[doc = "Bit 30 - Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller.??Software sets this field to the desired descriptor structure.??Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to ?1?.?Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING (?0?) and PONG (?1?). This field identifies the descriptor structure that is currently in use by the controller."]
    #[inline(always)]
    pub fn ping_pong(&mut self) -> PING_PONG_W {
        PING_PONG_W { w: self }
    }
    #[doc = "Bit 31 - ?0?: channel disabled. The channel?s trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. ??1?: channel enabled.??Software sets this field to ?1? to enable a specific channel.??Hardware sets this field to ?0? on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel?s descriptor structure)."]
    #[inline(always)]
    pub fn enabled(&mut self) -> ENABLED_W {
        ENABLED_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Channel control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch_ctl29](index.html) module"]
pub struct CH_CTL29_SPEC;
impl crate::RegisterSpec for CH_CTL29_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [ch_ctl29::R](R) reader structure"]
impl crate::Readable for CH_CTL29_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ch_ctl29::W](W) writer structure"]
impl crate::Writable for CH_CTL29_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CH_CTL29 to value 0"]
impl crate::Resettable for CH_CTL29_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
