#[doc = "Register `CFG31` reader"]
pub struct R(crate::R<CFG31_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG31_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG31_SPEC>> for R {
    fn from(reader: crate::R<CFG31_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG31` writer"]
pub struct W(crate::W<CFG31_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG31_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG31_SPEC>> for W {
    fn from(writer: crate::W<CFG31_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALT_RES_A {
    #[doc = "0: No description available"]
    COMPATIBLE = 0,
    #[doc = "1: No description available"]
    ALTERNATE = 1,
}
impl From<ALT_RES_A> for bool {
    #[inline(always)]
    fn from(variant: ALT_RES_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `ALT_RES` reader - This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs."]
pub struct ALT_RES_R(crate::FieldReader<bool, ALT_RES_A>);
impl ALT_RES_R {
    pub(crate) fn new(bits: bool) -> Self {
        ALT_RES_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> ALT_RES_A {
        match self.bits {
            false => ALT_RES_A::COMPATIBLE,
            true => ALT_RES_A::ALTERNATE,
        }
    }
    #[doc = "Checks if the value of the field is `COMPATIBLE`"]
    #[inline(always)]
    pub fn is_compatible(&self) -> bool {
        **self == ALT_RES_A::COMPATIBLE
    }
    #[doc = "Checks if the value of the field is `ALTERNATE`"]
    #[inline(always)]
    pub fn is_alternate(&self) -> bool {
        **self == ALT_RES_A::ALTERNATE
    }
}
impl core::ops::Deref for ALT_RES_R {
    type Target = crate::FieldReader<bool, ALT_RES_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ALT_RES` writer - This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs."]
pub struct ALT_RES_W<'a> {
    w: &'a mut W,
}
impl<'a> ALT_RES_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: ALT_RES_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn compatible(self) -> &'a mut W {
        self.variant(ALT_RES_A::COMPATIBLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn alternate(self) -> &'a mut W {
        self.variant(ALT_RES_A::ALTERNATE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01);
        self.w
    }
}
#[doc = "Enable synchronization of selected external clock\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXT_SYNC_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<EXT_SYNC_A> for bool {
    #[inline(always)]
    fn from(variant: EXT_SYNC_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `EXT_SYNC` reader - Enable synchronization of selected external clock"]
pub struct EXT_SYNC_R(crate::FieldReader<bool, EXT_SYNC_A>);
impl EXT_SYNC_R {
    pub(crate) fn new(bits: bool) -> Self {
        EXT_SYNC_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EXT_SYNC_A {
        match self.bits {
            false => EXT_SYNC_A::DISABLE,
            true => EXT_SYNC_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == EXT_SYNC_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == EXT_SYNC_A::ENABLE
    }
}
impl core::ops::Deref for EXT_SYNC_R {
    type Target = crate::FieldReader<bool, EXT_SYNC_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EXT_SYNC` writer - Enable synchronization of selected external clock"]
pub struct EXT_SYNC_W<'a> {
    w: &'a mut W,
}
impl<'a> EXT_SYNC_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EXT_SYNC_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(EXT_SYNC_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(EXT_SYNC_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1);
        self.w
    }
}
#[doc = "Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the status register.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EN_RES_STAT_A {
    #[doc = "0: No description available"]
    NEGATED = 0,
    #[doc = "1: No description available"]
    ASSERTED = 1,
}
impl From<EN_RES_STAT_A> for bool {
    #[inline(always)]
    fn from(variant: EN_RES_STAT_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `EN_RES_STAT` reader - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the status register."]
pub struct EN_RES_STAT_R(crate::FieldReader<bool, EN_RES_STAT_A>);
impl EN_RES_STAT_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_RES_STAT_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EN_RES_STAT_A {
        match self.bits {
            false => EN_RES_STAT_A::NEGATED,
            true => EN_RES_STAT_A::ASSERTED,
        }
    }
    #[doc = "Checks if the value of the field is `NEGATED`"]
    #[inline(always)]
    pub fn is_negated(&self) -> bool {
        **self == EN_RES_STAT_A::NEGATED
    }
    #[doc = "Checks if the value of the field is `ASSERTED`"]
    #[inline(always)]
    pub fn is_asserted(&self) -> bool {
        **self == EN_RES_STAT_A::ASSERTED
    }
}
impl core::ops::Deref for EN_RES_STAT_R {
    type Target = crate::FieldReader<bool, EN_RES_STAT_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_RES_STAT` writer - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the status register."]
pub struct EN_RES_STAT_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_RES_STAT_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EN_RES_STAT_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn negated(self) -> &'a mut W {
        self.variant(EN_RES_STAT_A::NEGATED)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn asserted(self) -> &'a mut W {
        self.variant(EN_RES_STAT_A::ASSERTED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
        self.w
    }
}
#[doc = "Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the Datapath block.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EN_RES_DP_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<EN_RES_DP_A> for bool {
    #[inline(always)]
    fn from(variant: EN_RES_DP_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `EN_RES_DP` reader - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the Datapath block."]
pub struct EN_RES_DP_R(crate::FieldReader<bool, EN_RES_DP_A>);
impl EN_RES_DP_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_RES_DP_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EN_RES_DP_A {
        match self.bits {
            false => EN_RES_DP_A::DISABLE,
            true => EN_RES_DP_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == EN_RES_DP_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == EN_RES_DP_A::ENABLE
    }
}
impl core::ops::Deref for EN_RES_DP_R {
    type Target = crate::FieldReader<bool, EN_RES_DP_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_RES_DP` writer - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the Datapath block."]
pub struct EN_RES_DP_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_RES_DP_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EN_RES_DP_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(EN_RES_DP_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(EN_RES_DP_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3);
        self.w
    }
}
#[doc = "External clock selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum EXT_CK_SEL_A {
    #[doc = "0: No description available"]
    RC_IN0 = 0,
    #[doc = "1: No description available"]
    RC_IN1 = 1,
    #[doc = "2: No description available"]
    RC_IN2 = 2,
    #[doc = "3: No description available"]
    RC_IN3 = 3,
}
impl From<EXT_CK_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: EXT_CK_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `EXT_CK_SEL` reader - External clock selection"]
pub struct EXT_CK_SEL_R(crate::FieldReader<u8, EXT_CK_SEL_A>);
impl EXT_CK_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        EXT_CK_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> EXT_CK_SEL_A {
        match self.bits {
            0 => EXT_CK_SEL_A::RC_IN0,
            1 => EXT_CK_SEL_A::RC_IN1,
            2 => EXT_CK_SEL_A::RC_IN2,
            3 => EXT_CK_SEL_A::RC_IN3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `RC_IN0`"]
    #[inline(always)]
    pub fn is_rc_in0(&self) -> bool {
        **self == EXT_CK_SEL_A::RC_IN0
    }
    #[doc = "Checks if the value of the field is `RC_IN1`"]
    #[inline(always)]
    pub fn is_rc_in1(&self) -> bool {
        **self == EXT_CK_SEL_A::RC_IN1
    }
    #[doc = "Checks if the value of the field is `RC_IN2`"]
    #[inline(always)]
    pub fn is_rc_in2(&self) -> bool {
        **self == EXT_CK_SEL_A::RC_IN2
    }
    #[doc = "Checks if the value of the field is `RC_IN3`"]
    #[inline(always)]
    pub fn is_rc_in3(&self) -> bool {
        **self == EXT_CK_SEL_A::RC_IN3
    }
}
impl core::ops::Deref for EXT_CK_SEL_R {
    type Target = crate::FieldReader<u8, EXT_CK_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EXT_CK_SEL` writer - External clock selection"]
pub struct EXT_CK_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> EXT_CK_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: EXT_CK_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in0(self) -> &'a mut W {
        self.variant(EXT_CK_SEL_A::RC_IN0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in1(self) -> &'a mut W {
        self.variant(EXT_CK_SEL_A::RC_IN1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in2(self) -> &'a mut W {
        self.variant(EXT_CK_SEL_A::RC_IN2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in3(self) -> &'a mut W {
        self.variant(EXT_CK_SEL_A::RC_IN3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4);
        self.w
    }
}
#[doc = "The meaning of this bit depends on the value of ALT RES. When ALT RES (CFG31) is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLD0_RES_POL_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<PLD0_RES_POL_A> for bool {
    #[inline(always)]
    fn from(variant: PLD0_RES_POL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `PLD0_RES_POL` reader - The meaning of this bit depends on the value of ALT RES. When ALT RES (CFG31) is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
pub struct PLD0_RES_POL_R(crate::FieldReader<bool, PLD0_RES_POL_A>);
impl PLD0_RES_POL_R {
    pub(crate) fn new(bits: bool) -> Self {
        PLD0_RES_POL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> PLD0_RES_POL_A {
        match self.bits {
            false => PLD0_RES_POL_A::NOINV,
            true => PLD0_RES_POL_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == PLD0_RES_POL_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == PLD0_RES_POL_A::INVERT
    }
}
impl core::ops::Deref for PLD0_RES_POL_R {
    type Target = crate::FieldReader<bool, PLD0_RES_POL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PLD0_RES_POL` writer - The meaning of this bit depends on the value of ALT RES. When ALT RES (CFG31) is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
pub struct PLD0_RES_POL_W<'a> {
    w: &'a mut W,
}
impl<'a> PLD0_RES_POL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLD0_RES_POL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(PLD0_RES_POL_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(PLD0_RES_POL_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
        self.w
    }
}
#[doc = "Not connected. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLD1_RES_POL_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<PLD1_RES_POL_A> for bool {
    #[inline(always)]
    fn from(variant: PLD1_RES_POL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `PLD1_RES_POL` reader - Not connected. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
pub struct PLD1_RES_POL_R(crate::FieldReader<bool, PLD1_RES_POL_A>);
impl PLD1_RES_POL_R {
    pub(crate) fn new(bits: bool) -> Self {
        PLD1_RES_POL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> PLD1_RES_POL_A {
        match self.bits {
            false => PLD1_RES_POL_A::NOINV,
            true => PLD1_RES_POL_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == PLD1_RES_POL_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == PLD1_RES_POL_A::INVERT
    }
}
impl core::ops::Deref for PLD1_RES_POL_R {
    type Target = crate::FieldReader<bool, PLD1_RES_POL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PLD1_RES_POL` writer - Not connected. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
pub struct PLD1_RES_POL_W<'a> {
    w: &'a mut W,
}
impl<'a> PLD1_RES_POL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLD1_RES_POL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(PLD1_RES_POL_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(PLD1_RES_POL_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7);
        self.w
    }
}
impl R {
    #[doc = "Bit 0 - This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs."]
    #[inline(always)]
    pub fn alt_res(&self) -> ALT_RES_R {
        ALT_RES_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Enable synchronization of selected external clock"]
    #[inline(always)]
    pub fn ext_sync(&self) -> EXT_SYNC_R {
        EXT_SYNC_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bit 2 - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the status register."]
    #[inline(always)]
    pub fn en_res_stat(&self) -> EN_RES_STAT_R {
        EN_RES_STAT_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the Datapath block."]
    #[inline(always)]
    pub fn en_res_dp(&self) -> EN_RES_DP_R {
        EN_RES_DP_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bits 4:5 - External clock selection"]
    #[inline(always)]
    pub fn ext_ck_sel(&self) -> EXT_CK_SEL_R {
        EXT_CK_SEL_R::new(((self.bits >> 4) & 0x03) as u8)
    }
    #[doc = "Bit 6 - The meaning of this bit depends on the value of ALT RES. When ALT RES (CFG31) is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
    #[inline(always)]
    pub fn pld0_res_pol(&self) -> PLD0_RES_POL_R {
        PLD0_RES_POL_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - Not connected. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
    #[inline(always)]
    pub fn pld1_res_pol(&self) -> PLD1_RES_POL_R {
        PLD1_RES_POL_R::new(((self.bits >> 7) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs."]
    #[inline(always)]
    pub fn alt_res(&mut self) -> ALT_RES_W {
        ALT_RES_W { w: self }
    }
    #[doc = "Bit 1 - Enable synchronization of selected external clock"]
    #[inline(always)]
    pub fn ext_sync(&mut self) -> EXT_SYNC_W {
        EXT_SYNC_W { w: self }
    }
    #[doc = "Bit 2 - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the status register."]
    #[inline(always)]
    pub fn en_res_stat(&mut self) -> EN_RES_STAT_W {
        EN_RES_STAT_W { w: self }
    }
    #[doc = "Bit 3 - Only valid when ALT RES (CFG31) is '1'. This bit gates the routed reset to the Datapath block."]
    #[inline(always)]
    pub fn en_res_dp(&mut self) -> EN_RES_DP_W {
        EN_RES_DP_W { w: self }
    }
    #[doc = "Bits 4:5 - External clock selection"]
    #[inline(always)]
    pub fn ext_ck_sel(&mut self) -> EXT_CK_SEL_W {
        EXT_CK_SEL_W { w: self }
    }
    #[doc = "Bit 6 - The meaning of this bit depends on the value of ALT RES. When ALT RES (CFG31) is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
    #[inline(always)]
    pub fn pld0_res_pol(&mut self) -> PLD0_RES_POL_W {
        PLD0_RES_POL_W { w: self }
    }
    #[doc = "Bit 7 - Not connected. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs."]
    #[inline(always)]
    pub fn pld1_res_pol(&mut self) -> PLD1_RES_POL_W {
        PLD1_RES_POL_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Reset control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg31](index.html) module"]
pub struct CFG31_SPEC;
impl crate::RegisterSpec for CFG31_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg31::R](R) reader structure"]
impl crate::Readable for CFG31_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg31::W](W) writer structure"]
impl crate::Writable for CFG31_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG31 to value 0"]
impl crate::Resettable for CFG31_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
