#[doc = "Register `CLK_IMO_TRIM4` reader"]
pub struct R(crate::R<CLK_IMO_TRIM4_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CLK_IMO_TRIM4_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CLK_IMO_TRIM4_SPEC>> for R {
    fn from(reader: crate::R<CLK_IMO_TRIM4_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CLK_IMO_TRIM4` writer"]
pub struct W(crate::W<CLK_IMO_TRIM4_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CLK_IMO_TRIM4_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CLK_IMO_TRIM4_SPEC>> for W {
    fn from(writer: crate::W<CLK_IMO_TRIM4_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `GAIN` reader - Gain for IMO. Typically stored in SFLASH and copied here on boot. Only used when locking IMO to an external source (USB mode or WCO DPLL), or when CLK_IMO_CONFIG.TEST_USB_MODE=1. ??Locking is initiated by the external peripheral providing the clock source (UDB or WCO). When locking is not enabled, the actual IMO gain is forced to a setting of 0.??SRSS directly supports a single locking peripheral. Two peripherals are supported when EXCO is included, selected with the OSCINTF_CTL.PORT_SEL register."]
pub struct GAIN_R(crate::FieldReader<u8, u8>);
impl GAIN_R {
    pub(crate) fn new(bits: u8) -> Self {
        GAIN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for GAIN_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `GAIN` writer - Gain for IMO. Typically stored in SFLASH and copied here on boot. Only used when locking IMO to an external source (USB mode or WCO DPLL), or when CLK_IMO_CONFIG.TEST_USB_MODE=1. ??Locking is initiated by the external peripheral providing the clock source (UDB or WCO). When locking is not enabled, the actual IMO gain is forced to a setting of 0.??SRSS directly supports a single locking peripheral. Two peripherals are supported when EXCO is included, selected with the OSCINTF_CTL.PORT_SEL register."]
pub struct GAIN_W<'a> {
    w: &'a mut W,
}
impl<'a> GAIN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
        self.w
    }
}
#[doc = "Field `FSOFFSET` reader - Fine Scale offset, providing two additional LSB bits to CLK_IMO_TRIM1.OFFSET when IMO is locking to an external source. ??Updated by hardware when locking is enabled. Can be updated by software when TEST_USB_MODE=1, otherwise writes are ignored."]
pub struct FSOFFSET_R(crate::FieldReader<u8, u8>);
impl FSOFFSET_R {
    pub(crate) fn new(bits: u8) -> Self {
        FSOFFSET_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for FSOFFSET_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FSOFFSET` writer - Fine Scale offset, providing two additional LSB bits to CLK_IMO_TRIM1.OFFSET when IMO is locking to an external source. ??Updated by hardware when locking is enabled. Can be updated by software when TEST_USB_MODE=1, otherwise writes are ignored."]
pub struct FSOFFSET_W<'a> {
    w: &'a mut W,
}
impl<'a> FSOFFSET_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:4 - Gain for IMO. Typically stored in SFLASH and copied here on boot. Only used when locking IMO to an external source (USB mode or WCO DPLL), or when CLK_IMO_CONFIG.TEST_USB_MODE=1. ??Locking is initiated by the external peripheral providing the clock source (UDB or WCO). When locking is not enabled, the actual IMO gain is forced to a setting of 0.??SRSS directly supports a single locking peripheral. Two peripherals are supported when EXCO is included, selected with the OSCINTF_CTL.PORT_SEL register."]
    #[inline(always)]
    pub fn gain(&self) -> GAIN_R {
        GAIN_R::new((self.bits & 0x1f) as u8)
    }
    #[doc = "Bits 5:7 - Fine Scale offset, providing two additional LSB bits to CLK_IMO_TRIM1.OFFSET when IMO is locking to an external source. ??Updated by hardware when locking is enabled. Can be updated by software when TEST_USB_MODE=1, otherwise writes are ignored."]
    #[inline(always)]
    pub fn fsoffset(&self) -> FSOFFSET_R {
        FSOFFSET_R::new(((self.bits >> 5) & 0x07) as u8)
    }
}
impl W {
    #[doc = "Bits 0:4 - Gain for IMO. Typically stored in SFLASH and copied here on boot. Only used when locking IMO to an external source (USB mode or WCO DPLL), or when CLK_IMO_CONFIG.TEST_USB_MODE=1. ??Locking is initiated by the external peripheral providing the clock source (UDB or WCO). When locking is not enabled, the actual IMO gain is forced to a setting of 0.??SRSS directly supports a single locking peripheral. Two peripherals are supported when EXCO is included, selected with the OSCINTF_CTL.PORT_SEL register."]
    #[inline(always)]
    pub fn gain(&mut self) -> GAIN_W {
        GAIN_W { w: self }
    }
    #[doc = "Bits 5:7 - Fine Scale offset, providing two additional LSB bits to CLK_IMO_TRIM1.OFFSET when IMO is locking to an external source. ??Updated by hardware when locking is enabled. Can be updated by software when TEST_USB_MODE=1, otherwise writes are ignored."]
    #[inline(always)]
    pub fn fsoffset(&mut self) -> FSOFFSET_W {
        FSOFFSET_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "IMO Trim Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_imo_trim4](index.html) module"]
pub struct CLK_IMO_TRIM4_SPEC;
impl crate::RegisterSpec for CLK_IMO_TRIM4_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [clk_imo_trim4::R](R) reader structure"]
impl crate::Readable for CLK_IMO_TRIM4_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [clk_imo_trim4::W](W) writer structure"]
impl crate::Writable for CLK_IMO_TRIM4_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CLK_IMO_TRIM4 to value 0"]
impl crate::Resettable for CLK_IMO_TRIM4_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
