#[doc = "Register `CFG22` reader"]
pub struct R(crate::R<CFG22_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG22_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG22_SPEC>> for R {
    fn from(reader: crate::R<CFG22_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG22` writer"]
pub struct W(crate::W<CFG22_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG22_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG22_SPEC>> for W {
    fn from(writer: crate::W<CFG22_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Selects the output source for the Status and Control routing connections\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum SC_OUT_CTL_A {
    #[doc = "0: No description available"]
    CONTROL = 0,
    #[doc = "1: No description available"]
    PARALLEL = 1,
    #[doc = "2: No description available"]
    COUNTER = 2,
}
impl From<SC_OUT_CTL_A> for u8 {
    #[inline(always)]
    fn from(variant: SC_OUT_CTL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `SC_OUT_CTL` reader - Selects the output source for the Status and Control routing connections"]
pub struct SC_OUT_CTL_R(crate::FieldReader<u8, SC_OUT_CTL_A>);
impl SC_OUT_CTL_R {
    pub(crate) fn new(bits: u8) -> Self {
        SC_OUT_CTL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SC_OUT_CTL_A {
        match self.bits {
            0 => SC_OUT_CTL_A::CONTROL,
            1 => SC_OUT_CTL_A::PARALLEL,
            2 => SC_OUT_CTL_A::COUNTER,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `CONTROL`"]
    #[inline(always)]
    pub fn is_control(&self) -> bool {
        **self == SC_OUT_CTL_A::CONTROL
    }
    #[doc = "Checks if the value of the field is `PARALLEL`"]
    #[inline(always)]
    pub fn is_parallel(&self) -> bool {
        **self == SC_OUT_CTL_A::PARALLEL
    }
    #[doc = "Checks if the value of the field is `COUNTER`"]
    #[inline(always)]
    pub fn is_counter(&self) -> bool {
        **self == SC_OUT_CTL_A::COUNTER
    }
}
impl core::ops::Deref for SC_OUT_CTL_R {
    type Target = crate::FieldReader<u8, SC_OUT_CTL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SC_OUT_CTL` writer - Selects the output source for the Status and Control routing connections"]
pub struct SC_OUT_CTL_W<'a> {
    w: &'a mut W,
}
impl<'a> SC_OUT_CTL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SC_OUT_CTL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn control(self) -> &'a mut W {
        self.variant(SC_OUT_CTL_A::CONTROL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn parallel(self) -> &'a mut W {
        self.variant(SC_OUT_CTL_A::PARALLEL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn counter(self) -> &'a mut W {
        self.variant(SC_OUT_CTL_A::COUNTER)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
        self.w
    }
}
#[doc = "SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SC_INT_MD_A {
    #[doc = "0: No description available"]
    NORMAL = 0,
    #[doc = "1: No description available"]
    INT_MODE = 1,
}
impl From<SC_INT_MD_A> for bool {
    #[inline(always)]
    fn from(variant: SC_INT_MD_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SC_INT_MD` reader - SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0"]
pub struct SC_INT_MD_R(crate::FieldReader<bool, SC_INT_MD_A>);
impl SC_INT_MD_R {
    pub(crate) fn new(bits: bool) -> Self {
        SC_INT_MD_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SC_INT_MD_A {
        match self.bits {
            false => SC_INT_MD_A::NORMAL,
            true => SC_INT_MD_A::INT_MODE,
        }
    }
    #[doc = "Checks if the value of the field is `NORMAL`"]
    #[inline(always)]
    pub fn is_normal(&self) -> bool {
        **self == SC_INT_MD_A::NORMAL
    }
    #[doc = "Checks if the value of the field is `INT_MODE`"]
    #[inline(always)]
    pub fn is_int_mode(&self) -> bool {
        **self == SC_INT_MD_A::INT_MODE
    }
}
impl core::ops::Deref for SC_INT_MD_R {
    type Target = crate::FieldReader<bool, SC_INT_MD_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SC_INT_MD` writer - SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0"]
pub struct SC_INT_MD_W<'a> {
    w: &'a mut W,
}
impl<'a> SC_INT_MD_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SC_INT_MD_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn normal(self) -> &'a mut W {
        self.variant(SC_INT_MD_A::NORMAL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn int_mode(self) -> &'a mut W {
        self.variant(SC_INT_MD_A::INT_MODE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
        self.w
    }
}
#[doc = "SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SC_SYNC_MD_A {
    #[doc = "0: No description available"]
    NORMAL = 0,
    #[doc = "1: No description available"]
    SYNC_MODE = 1,
}
impl From<SC_SYNC_MD_A> for bool {
    #[inline(always)]
    fn from(variant: SC_SYNC_MD_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SC_SYNC_MD` reader - SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module"]
pub struct SC_SYNC_MD_R(crate::FieldReader<bool, SC_SYNC_MD_A>);
impl SC_SYNC_MD_R {
    pub(crate) fn new(bits: bool) -> Self {
        SC_SYNC_MD_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SC_SYNC_MD_A {
        match self.bits {
            false => SC_SYNC_MD_A::NORMAL,
            true => SC_SYNC_MD_A::SYNC_MODE,
        }
    }
    #[doc = "Checks if the value of the field is `NORMAL`"]
    #[inline(always)]
    pub fn is_normal(&self) -> bool {
        **self == SC_SYNC_MD_A::NORMAL
    }
    #[doc = "Checks if the value of the field is `SYNC_MODE`"]
    #[inline(always)]
    pub fn is_sync_mode(&self) -> bool {
        **self == SC_SYNC_MD_A::SYNC_MODE
    }
}
impl core::ops::Deref for SC_SYNC_MD_R {
    type Target = crate::FieldReader<bool, SC_SYNC_MD_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SC_SYNC_MD` writer - SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module"]
pub struct SC_SYNC_MD_W<'a> {
    w: &'a mut W,
}
impl<'a> SC_SYNC_MD_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SC_SYNC_MD_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn normal(self) -> &'a mut W {
        self.variant(SC_SYNC_MD_A::NORMAL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync_mode(self) -> &'a mut W {
        self.variant(SC_SYNC_MD_A::SYNC_MODE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3);
        self.w
    }
}
#[doc = "Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SC_EXT_RES_A {
    #[doc = "0: No description available"]
    DISABLED = 0,
    #[doc = "1: No description available"]
    ENABLED = 1,
}
impl From<SC_EXT_RES_A> for bool {
    #[inline(always)]
    fn from(variant: SC_EXT_RES_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SC_EXT_RES` reader - Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware."]
pub struct SC_EXT_RES_R(crate::FieldReader<bool, SC_EXT_RES_A>);
impl SC_EXT_RES_R {
    pub(crate) fn new(bits: bool) -> Self {
        SC_EXT_RES_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SC_EXT_RES_A {
        match self.bits {
            false => SC_EXT_RES_A::DISABLED,
            true => SC_EXT_RES_A::ENABLED,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLED`"]
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        **self == SC_EXT_RES_A::DISABLED
    }
    #[doc = "Checks if the value of the field is `ENABLED`"]
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        **self == SC_EXT_RES_A::ENABLED
    }
}
impl core::ops::Deref for SC_EXT_RES_R {
    type Target = crate::FieldReader<bool, SC_EXT_RES_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SC_EXT_RES` writer - Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware."]
pub struct SC_EXT_RES_W<'a> {
    w: &'a mut W,
}
impl<'a> SC_EXT_RES_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SC_EXT_RES_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disabled(self) -> &'a mut W {
        self.variant(SC_EXT_RES_A::DISABLED)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enabled(self) -> &'a mut W {
        self.variant(SC_EXT_RES_A::ENABLED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - Selects the output source for the Status and Control routing connections"]
    #[inline(always)]
    pub fn sc_out_ctl(&self) -> SC_OUT_CTL_R {
        SC_OUT_CTL_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bit 2 - SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0"]
    #[inline(always)]
    pub fn sc_int_md(&self) -> SC_INT_MD_R {
        SC_INT_MD_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module"]
    #[inline(always)]
    pub fn sc_sync_md(&self) -> SC_SYNC_MD_R {
        SC_SYNC_MD_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 4 - Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware."]
    #[inline(always)]
    pub fn sc_ext_res(&self) -> SC_EXT_RES_R {
        SC_EXT_RES_R::new(((self.bits >> 4) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1 - Selects the output source for the Status and Control routing connections"]
    #[inline(always)]
    pub fn sc_out_ctl(&mut self) -> SC_OUT_CTL_W {
        SC_OUT_CTL_W { w: self }
    }
    #[doc = "Bit 2 - SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0"]
    #[inline(always)]
    pub fn sc_int_md(&mut self) -> SC_INT_MD_W {
        SC_INT_MD_W { w: self }
    }
    #[doc = "Bit 3 - SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module"]
    #[inline(always)]
    pub fn sc_sync_md(&mut self) -> SC_SYNC_MD_W {
        SC_SYNC_MD_W { w: self }
    }
    #[doc = "Bit 4 - Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware."]
    #[inline(always)]
    pub fn sc_ext_res(&mut self) -> SC_EXT_RES_W {
        SC_EXT_RES_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "SC block configuration control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg22](index.html) module"]
pub struct CFG22_SPEC;
impl crate::RegisterSpec for CFG22_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg22::R](R) reader structure"]
impl crate::Readable for CFG22_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg22::W](W) writer structure"]
impl crate::Writable for CFG22_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG22 to value 0"]
impl crate::Resettable for CFG22_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
