#[doc = "Register `PING_STATUS` reader"]
pub struct R(crate::R<PING_STATUS_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PING_STATUS_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PING_STATUS_SPEC>> for R {
    fn from(reader: crate::R<PING_STATUS_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PING_STATUS` writer"]
pub struct W(crate::W<PING_STATUS_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PING_STATUS_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PING_STATUS_SPEC>> for W {
    fn from(writer: crate::W<PING_STATUS_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `CURR_DATA_NR` reader - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:?- When a descriptor is done (RESPONSE is DONE), the field is set to \"0\" when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'.?- When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer.?- In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging.?HW only modifies this field for an active descriptor (STATUS.VALID to be ?1?). At descriptor initialization, SW should set this field to ?0?. ??This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses."]
pub struct CURR_DATA_NR_R(crate::FieldReader<u16, u16>);
impl CURR_DATA_NR_R {
    pub(crate) fn new(bits: u16) -> Self {
        CURR_DATA_NR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CURR_DATA_NR_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CURR_DATA_NR` writer - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:?- When a descriptor is done (RESPONSE is DONE), the field is set to \"0\" when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'.?- When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer.?- In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging.?HW only modifies this field for an active descriptor (STATUS.VALID to be ?1?). At descriptor initialization, SW should set this field to ?0?. ??This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses."]
pub struct CURR_DATA_NR_W<'a> {
    w: &'a mut W,
}
impl<'a> CURR_DATA_NR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
        self.w
    }
}
#[doc = "Field `RESPONSE` reader - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior).??0?/NO_ERROR: No error. Setting this response does NOT set the interrupt cause bit to ?1?. STATUS.VALID is NOT affected. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to ?0?/NO_ERROR during descriptor initialization.??1?/DONE: Descriptor is done (without errors). Setting this response sets the interrupt cause bit to ?1? if CONTROL.SET_CAUSE is ?1?. STATUS.VALID is set to ?0? if CONTROL.INV_DESCR is ?1?. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is updated if CONTROL.FLIPPING is ?1?.??2?/SRC_BUS_ERROR: Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??3?/DST_BUS_ERROR: Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??4?/SRC_MISAL: Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??5?/DST_MISAL: Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??6?/INVALID_DESCR: Invalid descriptor (STATUS.VALID is ?0?). This occurs when an activated channel has an invalid descriptor. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error)."]
pub struct RESPONSE_R(crate::FieldReader<u8, u8>);
impl RESPONSE_R {
    pub(crate) fn new(bits: u8) -> Self {
        RESPONSE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for RESPONSE_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RESPONSE` writer - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior).??0?/NO_ERROR: No error. Setting this response does NOT set the interrupt cause bit to ?1?. STATUS.VALID is NOT affected. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to ?0?/NO_ERROR during descriptor initialization.??1?/DONE: Descriptor is done (without errors). Setting this response sets the interrupt cause bit to ?1? if CONTROL.SET_CAUSE is ?1?. STATUS.VALID is set to ?0? if CONTROL.INV_DESCR is ?1?. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is updated if CONTROL.FLIPPING is ?1?.??2?/SRC_BUS_ERROR: Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??3?/DST_BUS_ERROR: Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??4?/SRC_MISAL: Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??5?/DST_MISAL: Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??6?/INVALID_DESCR: Invalid descriptor (STATUS.VALID is ?0?). This occurs when an activated channel has an invalid descriptor. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error)."]
pub struct RESPONSE_W<'a> {
    w: &'a mut W,
}
impl<'a> RESPONSE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
        self.w
    }
}
#[doc = "Field `VALID` reader - ?0?: Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to ?1?).??1?: Valid.??Hardware set this field to ?0? when a descriptor is done, but only if CONTROL.INV_DESCR is ?1?.??Software sets this field to ?1? when a descriptor is initialized."]
pub struct VALID_R(crate::FieldReader<bool, bool>);
impl VALID_R {
    pub(crate) fn new(bits: bool) -> Self {
        VALID_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for VALID_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `VALID` writer - ?0?: Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to ?1?).??1?: Valid.??Hardware set this field to ?0? when a descriptor is done, but only if CONTROL.INV_DESCR is ?1?.??Software sets this field to ?1? when a descriptor is initialized."]
pub struct VALID_W<'a> {
    w: &'a mut W,
}
impl<'a> VALID_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:15 - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:?- When a descriptor is done (RESPONSE is DONE), the field is set to \"0\" when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'.?- When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer.?- In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging.?HW only modifies this field for an active descriptor (STATUS.VALID to be ?1?). At descriptor initialization, SW should set this field to ?0?. ??This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses."]
    #[inline(always)]
    pub fn curr_data_nr(&self) -> CURR_DATA_NR_R {
        CURR_DATA_NR_R::new((self.bits & 0xffff) as u16)
    }
    #[doc = "Bits 16:18 - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior).??0?/NO_ERROR: No error. Setting this response does NOT set the interrupt cause bit to ?1?. STATUS.VALID is NOT affected. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to ?0?/NO_ERROR during descriptor initialization.??1?/DONE: Descriptor is done (without errors). Setting this response sets the interrupt cause bit to ?1? if CONTROL.SET_CAUSE is ?1?. STATUS.VALID is set to ?0? if CONTROL.INV_DESCR is ?1?. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is updated if CONTROL.FLIPPING is ?1?.??2?/SRC_BUS_ERROR: Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??3?/DST_BUS_ERROR: Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??4?/SRC_MISAL: Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??5?/DST_MISAL: Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??6?/INVALID_DESCR: Invalid descriptor (STATUS.VALID is ?0?). This occurs when an activated channel has an invalid descriptor. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error)."]
    #[inline(always)]
    pub fn response(&self) -> RESPONSE_R {
        RESPONSE_R::new(((self.bits >> 16) & 0x07) as u8)
    }
    #[doc = "Bit 31 - ?0?: Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to ?1?).??1?: Valid.??Hardware set this field to ?0? when a descriptor is done, but only if CONTROL.INV_DESCR is ?1?.??Software sets this field to ?1? when a descriptor is initialized."]
    #[inline(always)]
    pub fn valid(&self) -> VALID_R {
        VALID_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:15 - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:?- When a descriptor is done (RESPONSE is DONE), the field is set to \"0\" when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'.?- When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer.?- In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging.?HW only modifies this field for an active descriptor (STATUS.VALID to be ?1?). At descriptor initialization, SW should set this field to ?0?. ??This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses."]
    #[inline(always)]
    pub fn curr_data_nr(&mut self) -> CURR_DATA_NR_W {
        CURR_DATA_NR_W { w: self }
    }
    #[doc = "Bits 16:18 - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior).??0?/NO_ERROR: No error. Setting this response does NOT set the interrupt cause bit to ?1?. STATUS.VALID is NOT affected. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to ?0?/NO_ERROR during descriptor initialization.??1?/DONE: Descriptor is done (without errors). Setting this response sets the interrupt cause bit to ?1? if CONTROL.SET_CAUSE is ?1?. STATUS.VALID is set to ?0? if CONTROL.INV_DESCR is ?1?. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is updated if CONTROL.FLIPPING is ?1?.??2?/SRC_BUS_ERROR: Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??3?/DST_BUS_ERROR: Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??4?/SRC_MISAL: Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??5?/DST_MISAL: Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to ?1?. STATUS.VALID is set ?0?. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error).??6?/INVALID_DESCR: Invalid descriptor (STATUS.VALID is ?0?). This occurs when an activated channel has an invalid descriptor. CHi_CTL.ENABLED is set to ?0?. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error)."]
    #[inline(always)]
    pub fn response(&mut self) -> RESPONSE_W {
        RESPONSE_W { w: self }
    }
    #[doc = "Bit 31 - ?0?: Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to ?1?).??1?: Valid.??Hardware set this field to ?0? when a descriptor is done, but only if CONTROL.INV_DESCR is ?1?.??Software sets this field to ?1? when a descriptor is initialized."]
    #[inline(always)]
    pub fn valid(&mut self) -> VALID_W {
        VALID_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Ping status word\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ping_status](index.html) module"]
pub struct PING_STATUS_SPEC;
impl crate::RegisterSpec for PING_STATUS_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [ping_status::R](R) reader structure"]
impl crate::Readable for PING_STATUS_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ping_status::W](W) writer structure"]
impl crate::Writable for PING_STATUS_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PING_STATUS to value 0"]
impl crate::Resettable for PING_STATUS_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
