#[doc = "Register `ADDR` reader"]
pub struct R(crate::R<ADDR_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<ADDR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<ADDR_SPEC>> for R {
    fn from(reader: crate::R<ADDR_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `ADDR` writer"]
pub struct W(crate::W<ADDR_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<ADDR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<ADDR_SPEC>> for W {
    fn from(writer: crate::W<ADDR_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PRESENT` reader - Entry present."]
pub struct PRESENT_R(crate::FieldReader<bool, bool>);
impl PRESENT_R {
    pub(crate) fn new(bits: bool) -> Self {
        PRESENT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PRESENT_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FORMAT_32BIT` reader - ROM Table format:?'0: 8-bit format.?'1': 32-bit format."]
pub struct FORMAT_32BIT_R(crate::FieldReader<bool, bool>);
impl FORMAT_32BIT_R {
    pub(crate) fn new(bits: bool) -> Self {
        FORMAT_32BIT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for FORMAT_32BIT_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ADDR_OFFSET` reader - Address offset of the Cortex-M0 ROM Table base address (0xe00f:f000) wrt. Cypress chip specific ROM Table base address (0xf000:0000). ADDR_OFFSET\\[19:0\\]
= 0xe00f:f - 0xf000:0 = 0xf00f:f."]
pub struct ADDR_OFFSET_R(crate::FieldReader<u32, u32>);
impl ADDR_OFFSET_R {
    pub(crate) fn new(bits: u32) -> Self {
        ADDR_OFFSET_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ADDR_OFFSET_R {
    type Target = crate::FieldReader<u32, u32>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl R {
    #[doc = "Bit 0 - Entry present."]
    #[inline(always)]
    pub fn present(&self) -> PRESENT_R {
        PRESENT_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - ROM Table format:?'0: 8-bit format.?'1': 32-bit format."]
    #[inline(always)]
    pub fn format_32bit(&self) -> FORMAT_32BIT_R {
        FORMAT_32BIT_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bits 12:31 - Address offset of the Cortex-M0 ROM Table base address (0xe00f:f000) wrt. Cypress chip specific ROM Table base address (0xf000:0000). ADDR_OFFSET\\[19:0\\]
= 0xe00f:f - 0xf000:0 = 0xf00f:f."]
    #[inline(always)]
    pub fn addr_offset(&self) -> ADDR_OFFSET_R {
        ADDR_OFFSET_R::new(((self.bits >> 12) & 0x000f_ffff) as u32)
    }
}
impl W {
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Link to Cortex M0 ROM Table.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"]
pub struct ADDR_SPEC;
impl crate::RegisterSpec for ADDR_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [addr::R](R) reader structure"]
impl crate::Readable for ADDR_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"]
impl crate::Writable for ADDR_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets ADDR to value 0"]
impl crate::Resettable for ADDR_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
