#[doc = "Register `CTRL` reader"]
pub struct R(crate::R<CTRL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CTRL_SPEC>> for R {
    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CTRL` writer"]
pub struct W(crate::W<CTRL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CTRL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CTRL_SPEC>> for W {
    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `COUNTER_ENABLED` reader - Counter enables for counters 0 up to CNT_NR-1.?'0': counter disabled.?'1': counter enabled.?Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:?- the associated counter triggers in the CMD register are set to '0'.?- the counter's interrupt cause fields in counter's INTR register.?- the counter's status fields in counter's STATUS register..?- the counter's trigger outputs (\"tr_overflow\", \"tr_underflow\" and \"tr_compare_match\").?- the counter's line outputs (\"line_out\" and \"line_compl_out\")."]
pub struct COUNTER_ENABLED_R(crate::FieldReader<u8, u8>);
impl COUNTER_ENABLED_R {
    pub(crate) fn new(bits: u8) -> Self {
        COUNTER_ENABLED_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for COUNTER_ENABLED_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `COUNTER_ENABLED` writer - Counter enables for counters 0 up to CNT_NR-1.?'0': counter disabled.?'1': counter enabled.?Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:?- the associated counter triggers in the CMD register are set to '0'.?- the counter's interrupt cause fields in counter's INTR register.?- the counter's status fields in counter's STATUS register..?- the counter's trigger outputs (\"tr_overflow\", \"tr_underflow\" and \"tr_compare_match\").?- the counter's line outputs (\"line_out\" and \"line_compl_out\")."]
pub struct COUNTER_ENABLED_W<'a> {
    w: &'a mut W,
}
impl<'a> COUNTER_ENABLED_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:7 - Counter enables for counters 0 up to CNT_NR-1.?'0': counter disabled.?'1': counter enabled.?Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:?- the associated counter triggers in the CMD register are set to '0'.?- the counter's interrupt cause fields in counter's INTR register.?- the counter's status fields in counter's STATUS register..?- the counter's trigger outputs (\"tr_overflow\", \"tr_underflow\" and \"tr_compare_match\").?- the counter's line outputs (\"line_out\" and \"line_compl_out\")."]
    #[inline(always)]
    pub fn counter_enabled(&self) -> COUNTER_ENABLED_R {
        COUNTER_ENABLED_R::new((self.bits & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bits 0:7 - Counter enables for counters 0 up to CNT_NR-1.?'0': counter disabled.?'1': counter enabled.?Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:?- the associated counter triggers in the CMD register are set to '0'.?- the counter's interrupt cause fields in counter's INTR register.?- the counter's status fields in counter's STATUS register..?- the counter's trigger outputs (\"tr_overflow\", \"tr_underflow\" and \"tr_compare_match\").?- the counter's line outputs (\"line_out\" and \"line_compl_out\")."]
    #[inline(always)]
    pub fn counter_enabled(&mut self) -> COUNTER_ENABLED_W {
        COUNTER_ENABLED_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "TCPWM control register 0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
pub struct CTRL_SPEC;
impl crate::RegisterSpec for CTRL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
impl crate::Readable for CTRL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
impl crate::Writable for CTRL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CTRL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
