#[doc = "Register `TOPSEL_L` reader"]
pub struct R(crate::R<TOPSEL_L_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<TOPSEL_L_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<TOPSEL_L_SPEC>> for R {
    fn from(reader: crate::R<TOPSEL_L_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `TOPSEL_L` writer"]
pub struct W(crate::W<TOPSEL_L_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<TOPSEL_L_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<TOPSEL_L_SPEC>> for W {
    fn from(writer: crate::W<TOPSEL_L_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Clock selection control for digital clock\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CLK_SEL0_A {
    #[doc = "0: No description available"]
    EDGE_ENABLES = 0,
    #[doc = "1: No description available"]
    PORT_INPUT = 1,
    #[doc = "2: No description available"]
    DSI_OUTPUT = 2,
    #[doc = "3: No description available"]
    SYNC_DSI_OUTPUT = 3,
}
impl From<CLK_SEL0_A> for u8 {
    #[inline(always)]
    fn from(variant: CLK_SEL0_A) -> Self {
        variant as _
    }
}
#[doc = "Field `CLK_SEL0` reader - Clock selection control for digital clock"]
pub struct CLK_SEL0_R(crate::FieldReader<u8, CLK_SEL0_A>);
impl CLK_SEL0_R {
    pub(crate) fn new(bits: u8) -> Self {
        CLK_SEL0_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CLK_SEL0_A {
        match self.bits {
            0 => CLK_SEL0_A::EDGE_ENABLES,
            1 => CLK_SEL0_A::PORT_INPUT,
            2 => CLK_SEL0_A::DSI_OUTPUT,
            3 => CLK_SEL0_A::SYNC_DSI_OUTPUT,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `EDGE_ENABLES`"]
    #[inline(always)]
    pub fn is_edge_enables(&self) -> bool {
        **self == CLK_SEL0_A::EDGE_ENABLES
    }
    #[doc = "Checks if the value of the field is `PORT_INPUT`"]
    #[inline(always)]
    pub fn is_port_input(&self) -> bool {
        **self == CLK_SEL0_A::PORT_INPUT
    }
    #[doc = "Checks if the value of the field is `DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_dsi_output(&self) -> bool {
        **self == CLK_SEL0_A::DSI_OUTPUT
    }
    #[doc = "Checks if the value of the field is `SYNC_DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_sync_dsi_output(&self) -> bool {
        **self == CLK_SEL0_A::SYNC_DSI_OUTPUT
    }
}
impl core::ops::Deref for CLK_SEL0_R {
    type Target = crate::FieldReader<u8, CLK_SEL0_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CLK_SEL0` writer - Clock selection control for digital clock"]
pub struct CLK_SEL0_W<'a> {
    w: &'a mut W,
}
impl<'a> CLK_SEL0_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CLK_SEL0_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn edge_enables(self) -> &'a mut W {
        self.variant(CLK_SEL0_A::EDGE_ENABLES)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn port_input(self) -> &'a mut W {
        self.variant(CLK_SEL0_A::PORT_INPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL0_A::DSI_OUTPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync_dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL0_A::SYNC_DSI_OUTPUT)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
        self.w
    }
}
#[doc = "Clock selection control for digital clock\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CLK_SEL1_A {
    #[doc = "0: No description available"]
    EDGE_ENABLES = 0,
    #[doc = "1: No description available"]
    PORT_INPUT = 1,
    #[doc = "2: No description available"]
    DSI_OUTPUT = 2,
    #[doc = "3: No description available"]
    SYNC_DSI_OUTPUT = 3,
}
impl From<CLK_SEL1_A> for u8 {
    #[inline(always)]
    fn from(variant: CLK_SEL1_A) -> Self {
        variant as _
    }
}
#[doc = "Field `CLK_SEL1` reader - Clock selection control for digital clock"]
pub struct CLK_SEL1_R(crate::FieldReader<u8, CLK_SEL1_A>);
impl CLK_SEL1_R {
    pub(crate) fn new(bits: u8) -> Self {
        CLK_SEL1_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CLK_SEL1_A {
        match self.bits {
            0 => CLK_SEL1_A::EDGE_ENABLES,
            1 => CLK_SEL1_A::PORT_INPUT,
            2 => CLK_SEL1_A::DSI_OUTPUT,
            3 => CLK_SEL1_A::SYNC_DSI_OUTPUT,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `EDGE_ENABLES`"]
    #[inline(always)]
    pub fn is_edge_enables(&self) -> bool {
        **self == CLK_SEL1_A::EDGE_ENABLES
    }
    #[doc = "Checks if the value of the field is `PORT_INPUT`"]
    #[inline(always)]
    pub fn is_port_input(&self) -> bool {
        **self == CLK_SEL1_A::PORT_INPUT
    }
    #[doc = "Checks if the value of the field is `DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_dsi_output(&self) -> bool {
        **self == CLK_SEL1_A::DSI_OUTPUT
    }
    #[doc = "Checks if the value of the field is `SYNC_DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_sync_dsi_output(&self) -> bool {
        **self == CLK_SEL1_A::SYNC_DSI_OUTPUT
    }
}
impl core::ops::Deref for CLK_SEL1_R {
    type Target = crate::FieldReader<u8, CLK_SEL1_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CLK_SEL1` writer - Clock selection control for digital clock"]
pub struct CLK_SEL1_W<'a> {
    w: &'a mut W,
}
impl<'a> CLK_SEL1_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CLK_SEL1_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn edge_enables(self) -> &'a mut W {
        self.variant(CLK_SEL1_A::EDGE_ENABLES)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn port_input(self) -> &'a mut W {
        self.variant(CLK_SEL1_A::PORT_INPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL1_A::DSI_OUTPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync_dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL1_A::SYNC_DSI_OUTPUT)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2);
        self.w
    }
}
#[doc = "Clock selection control for digital clock\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CLK_SEL2_A {
    #[doc = "0: No description available"]
    EDGE_ENABLES = 0,
    #[doc = "1: No description available"]
    PORT_INPUT = 1,
    #[doc = "2: No description available"]
    DSI_OUTPUT = 2,
    #[doc = "3: No description available"]
    SYNC_DSI_OUTPUT = 3,
}
impl From<CLK_SEL2_A> for u8 {
    #[inline(always)]
    fn from(variant: CLK_SEL2_A) -> Self {
        variant as _
    }
}
#[doc = "Field `CLK_SEL2` reader - Clock selection control for digital clock"]
pub struct CLK_SEL2_R(crate::FieldReader<u8, CLK_SEL2_A>);
impl CLK_SEL2_R {
    pub(crate) fn new(bits: u8) -> Self {
        CLK_SEL2_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CLK_SEL2_A {
        match self.bits {
            0 => CLK_SEL2_A::EDGE_ENABLES,
            1 => CLK_SEL2_A::PORT_INPUT,
            2 => CLK_SEL2_A::DSI_OUTPUT,
            3 => CLK_SEL2_A::SYNC_DSI_OUTPUT,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `EDGE_ENABLES`"]
    #[inline(always)]
    pub fn is_edge_enables(&self) -> bool {
        **self == CLK_SEL2_A::EDGE_ENABLES
    }
    #[doc = "Checks if the value of the field is `PORT_INPUT`"]
    #[inline(always)]
    pub fn is_port_input(&self) -> bool {
        **self == CLK_SEL2_A::PORT_INPUT
    }
    #[doc = "Checks if the value of the field is `DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_dsi_output(&self) -> bool {
        **self == CLK_SEL2_A::DSI_OUTPUT
    }
    #[doc = "Checks if the value of the field is `SYNC_DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_sync_dsi_output(&self) -> bool {
        **self == CLK_SEL2_A::SYNC_DSI_OUTPUT
    }
}
impl core::ops::Deref for CLK_SEL2_R {
    type Target = crate::FieldReader<u8, CLK_SEL2_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CLK_SEL2` writer - Clock selection control for digital clock"]
pub struct CLK_SEL2_W<'a> {
    w: &'a mut W,
}
impl<'a> CLK_SEL2_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CLK_SEL2_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn edge_enables(self) -> &'a mut W {
        self.variant(CLK_SEL2_A::EDGE_ENABLES)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn port_input(self) -> &'a mut W {
        self.variant(CLK_SEL2_A::PORT_INPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL2_A::DSI_OUTPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync_dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL2_A::SYNC_DSI_OUTPUT)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4);
        self.w
    }
}
#[doc = "Clock selection control for digital clock\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CLK_SEL3_A {
    #[doc = "0: No description available"]
    EDGE_ENABLES = 0,
    #[doc = "1: No description available"]
    PORT_INPUT = 1,
    #[doc = "2: No description available"]
    DSI_OUTPUT = 2,
    #[doc = "3: No description available"]
    SYNC_DSI_OUTPUT = 3,
}
impl From<CLK_SEL3_A> for u8 {
    #[inline(always)]
    fn from(variant: CLK_SEL3_A) -> Self {
        variant as _
    }
}
#[doc = "Field `CLK_SEL3` reader - Clock selection control for digital clock"]
pub struct CLK_SEL3_R(crate::FieldReader<u8, CLK_SEL3_A>);
impl CLK_SEL3_R {
    pub(crate) fn new(bits: u8) -> Self {
        CLK_SEL3_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CLK_SEL3_A {
        match self.bits {
            0 => CLK_SEL3_A::EDGE_ENABLES,
            1 => CLK_SEL3_A::PORT_INPUT,
            2 => CLK_SEL3_A::DSI_OUTPUT,
            3 => CLK_SEL3_A::SYNC_DSI_OUTPUT,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `EDGE_ENABLES`"]
    #[inline(always)]
    pub fn is_edge_enables(&self) -> bool {
        **self == CLK_SEL3_A::EDGE_ENABLES
    }
    #[doc = "Checks if the value of the field is `PORT_INPUT`"]
    #[inline(always)]
    pub fn is_port_input(&self) -> bool {
        **self == CLK_SEL3_A::PORT_INPUT
    }
    #[doc = "Checks if the value of the field is `DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_dsi_output(&self) -> bool {
        **self == CLK_SEL3_A::DSI_OUTPUT
    }
    #[doc = "Checks if the value of the field is `SYNC_DSI_OUTPUT`"]
    #[inline(always)]
    pub fn is_sync_dsi_output(&self) -> bool {
        **self == CLK_SEL3_A::SYNC_DSI_OUTPUT
    }
}
impl core::ops::Deref for CLK_SEL3_R {
    type Target = crate::FieldReader<u8, CLK_SEL3_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CLK_SEL3` writer - Clock selection control for digital clock"]
pub struct CLK_SEL3_W<'a> {
    w: &'a mut W,
}
impl<'a> CLK_SEL3_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CLK_SEL3_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn edge_enables(self) -> &'a mut W {
        self.variant(CLK_SEL3_A::EDGE_ENABLES)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn port_input(self) -> &'a mut W {
        self.variant(CLK_SEL3_A::PORT_INPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL3_A::DSI_OUTPUT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync_dsi_output(self) -> &'a mut W {
        self.variant(CLK_SEL3_A::SYNC_DSI_OUTPUT)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u8 & 0x03) << 6);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel0(&self) -> CLK_SEL0_R {
        CLK_SEL0_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bits 2:3 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel1(&self) -> CLK_SEL1_R {
        CLK_SEL1_R::new(((self.bits >> 2) & 0x03) as u8)
    }
    #[doc = "Bits 4:5 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel2(&self) -> CLK_SEL2_R {
        CLK_SEL2_R::new(((self.bits >> 4) & 0x03) as u8)
    }
    #[doc = "Bits 6:7 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel3(&self) -> CLK_SEL3_R {
        CLK_SEL3_R::new(((self.bits >> 6) & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bits 0:1 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel0(&mut self) -> CLK_SEL0_W {
        CLK_SEL0_W { w: self }
    }
    #[doc = "Bits 2:3 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel1(&mut self) -> CLK_SEL1_W {
        CLK_SEL1_W { w: self }
    }
    #[doc = "Bits 4:5 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel2(&mut self) -> CLK_SEL2_W {
        CLK_SEL2_W { w: self }
    }
    #[doc = "Bits 6:7 - Clock selection control for digital clock"]
    #[inline(always)]
    pub fn clk_sel3(&mut self) -> CLK_SEL3_W {
        CLK_SEL3_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Lower Nibble Top Digital Clock Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [topsel_l](index.html) module"]
pub struct TOPSEL_L_SPEC;
impl crate::RegisterSpec for TOPSEL_L_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [topsel_l::R](R) reader structure"]
impl crate::Readable for TOPSEL_L_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [topsel_l::W](W) writer structure"]
impl crate::Writable for TOPSEL_L_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets TOPSEL_L to value 0"]
impl crate::Resettable for TOPSEL_L_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
