#[doc = "Register `PING_CTL` reader"]
pub struct R(crate::R<PING_CTL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PING_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PING_CTL_SPEC>> for R {
    fn from(reader: crate::R<PING_CTL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PING_CTL` writer"]
pub struct W(crate::W<PING_CTL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PING_CTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PING_CTL_SPEC>> for W {
    fn from(writer: crate::W<PING_CTL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `DATA_NR` reader - Number of data elements that are transferred by a single descriptor.?In DW mode (OPCODE is ?0?) each trigger initiates the transfer of a single data element. This field specifies the source and/or destination buffer size in data elements: buffer size = DATA_NR+1. The buffer is typically associated to a memory structure.?In DMA mode (OPCODE is ?1? or ?2?) each trigger initiates the transfer of DATA_NR+1 data elements."]
pub struct DATA_NR_R(crate::FieldReader<u16, u16>);
impl DATA_NR_R {
    pub(crate) fn new(bits: u16) -> Self {
        DATA_NR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DATA_NR_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DATA_NR` writer - Number of data elements that are transferred by a single descriptor.?In DW mode (OPCODE is ?0?) each trigger initiates the transfer of a single data element. This field specifies the source and/or destination buffer size in data elements: buffer size = DATA_NR+1. The buffer is typically associated to a memory structure.?In DMA mode (OPCODE is ?1? or ?2?) each trigger initiates the transfer of DATA_NR+1 data elements."]
pub struct DATA_NR_W<'a> {
    w: &'a mut W,
}
impl<'a> DATA_NR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
        self.w
    }
}
#[doc = "Field `DATA_SIZE` reader - Specifies the data element size:??0?: Byte (8 bits).??1?: Halfword (16 bits).??2?: Word (32 bits).?DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:?- DATA is 8 bit, SRC is 8 bit, DST is 8 bit?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit?- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 16 bit, SRC is 16 bit, DST is 16 bit?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit?- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 32 bit, SRC is 32 bit, DST is 32 bit"]
pub struct DATA_SIZE_R(crate::FieldReader<u8, u8>);
impl DATA_SIZE_R {
    pub(crate) fn new(bits: u8) -> Self {
        DATA_SIZE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DATA_SIZE_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DATA_SIZE` writer - Specifies the data element size:??0?: Byte (8 bits).??1?: Halfword (16 bits).??2?: Word (32 bits).?DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:?- DATA is 8 bit, SRC is 8 bit, DST is 8 bit?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit?- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 16 bit, SRC is 16 bit, DST is 16 bit?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit?- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 32 bit, SRC is 32 bit, DST is 32 bit"]
pub struct DATA_SIZE_W<'a> {
    w: &'a mut W,
}
impl<'a> DATA_SIZE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
        self.w
    }
}
#[doc = "Field `DST_TRANSFER_SIZE` reader - Specifies the bus transfer size to the destination location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element."]
pub struct DST_TRANSFER_SIZE_R(crate::FieldReader<bool, bool>);
impl DST_TRANSFER_SIZE_R {
    pub(crate) fn new(bits: bool) -> Self {
        DST_TRANSFER_SIZE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DST_TRANSFER_SIZE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DST_TRANSFER_SIZE` writer - Specifies the bus transfer size to the destination location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element."]
pub struct DST_TRANSFER_SIZE_W<'a> {
    w: &'a mut W,
}
impl<'a> DST_TRANSFER_SIZE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
        self.w
    }
}
#[doc = "Field `DST_ADDR_INCR` reader - Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not.??0? : No increment, typically used for transmit (TX) FIFO structures.??1?: Increment, typically used for memory structures."]
pub struct DST_ADDR_INCR_R(crate::FieldReader<bool, bool>);
impl DST_ADDR_INCR_R {
    pub(crate) fn new(bits: bool) -> Self {
        DST_ADDR_INCR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DST_ADDR_INCR_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DST_ADDR_INCR` writer - Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not.??0? : No increment, typically used for transmit (TX) FIFO structures.??1?: Increment, typically used for memory structures."]
pub struct DST_ADDR_INCR_W<'a> {
    w: &'a mut W,
}
impl<'a> DST_ADDR_INCR_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
        self.w
    }
}
#[doc = "Field `SRC_TRANSFER_SIZE` reader - Specifies the bus transfer size to the source location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element."]
pub struct SRC_TRANSFER_SIZE_R(crate::FieldReader<bool, bool>);
impl SRC_TRANSFER_SIZE_R {
    pub(crate) fn new(bits: bool) -> Self {
        SRC_TRANSFER_SIZE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for SRC_TRANSFER_SIZE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SRC_TRANSFER_SIZE` writer - Specifies the bus transfer size to the source location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element."]
pub struct SRC_TRANSFER_SIZE_W<'a> {
    w: &'a mut W,
}
impl<'a> SRC_TRANSFER_SIZE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
        self.w
    }
}
#[doc = "Field `SRC_ADDR_INCR` reader - Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not.??0?: No increment, typically used for receive (RX) FIFO structures.??1?: Increment, typically used for memory structures."]
pub struct SRC_ADDR_INCR_R(crate::FieldReader<bool, bool>);
impl SRC_ADDR_INCR_R {
    pub(crate) fn new(bits: bool) -> Self {
        SRC_ADDR_INCR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for SRC_ADDR_INCR_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SRC_ADDR_INCR` writer - Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not.??0?: No increment, typically used for receive (RX) FIFO structures.??1?: Increment, typically used for memory structures."]
pub struct SRC_ADDR_INCR_W<'a> {
    w: &'a mut W,
}
impl<'a> SRC_ADDR_INCR_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
        self.w
    }
}
#[doc = "Field `WAIT_FOR_DEACT` reader - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller?s data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent?s trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to \"0\"). The wait cycles incurred by this field reduce DW/DMA controller performance.??0?: Do not wait for de-activation (for pulse sensitive triggers).??1?: Wait for up to 4 cycles.??2?: Wait for up to 8 cycles.??3?: Wait indefinitely. This option may result in DW/DMA controller lockup if the system trigger is not de-activated by the source agent."]
pub struct WAIT_FOR_DEACT_R(crate::FieldReader<u8, u8>);
impl WAIT_FOR_DEACT_R {
    pub(crate) fn new(bits: u8) -> Self {
        WAIT_FOR_DEACT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for WAIT_FOR_DEACT_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `WAIT_FOR_DEACT` writer - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller?s data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent?s trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to \"0\"). The wait cycles incurred by this field reduce DW/DMA controller performance.??0?: Do not wait for de-activation (for pulse sensitive triggers).??1?: Wait for up to 4 cycles.??2?: Wait for up to 8 cycles.??3?: Wait indefinitely. This option may result in DW/DMA controller lockup if the system trigger is not de-activated by the source agent."]
pub struct WAIT_FOR_DEACT_W<'a> {
    w: &'a mut W,
}
impl<'a> WAIT_FOR_DEACT_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24);
        self.w
    }
}
#[doc = "Field `INV_DESCR` reader - ?1?: On completion of the current descriptor structure, the VALID bit of the descriptor?s STATUS word is set to ?0?."]
pub struct INV_DESCR_R(crate::FieldReader<bool, bool>);
impl INV_DESCR_R {
    pub(crate) fn new(bits: bool) -> Self {
        INV_DESCR_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for INV_DESCR_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `INV_DESCR` writer - ?1?: On completion of the current descriptor structure, the VALID bit of the descriptor?s STATUS word is set to ?0?."]
pub struct INV_DESCR_W<'a> {
    w: &'a mut W,
}
impl<'a> INV_DESCR_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
        self.w
    }
}
#[doc = "Field `SET_CAUSE` reader - ?1?: On completion of the current descriptor structure, the interrupt cause field of the channel is set to ?1? (INTR.CH\\[i\\])."]
pub struct SET_CAUSE_R(crate::FieldReader<bool, bool>);
impl SET_CAUSE_R {
    pub(crate) fn new(bits: bool) -> Self {
        SET_CAUSE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for SET_CAUSE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SET_CAUSE` writer - ?1?: On completion of the current descriptor structure, the interrupt cause field of the channel is set to ?1? (INTR.CH\\[i\\])."]
pub struct SET_CAUSE_W<'a> {
    w: &'a mut W,
}
impl<'a> SET_CAUSE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
        self.w
    }
}
#[doc = "Field `PREEMPTABLE` reader - ?1?: Transfer is preemptable. In DMA mode (OPCODE is ?1? or ?2?), multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled."]
pub struct PREEMPTABLE_R(crate::FieldReader<bool, bool>);
impl PREEMPTABLE_R {
    pub(crate) fn new(bits: bool) -> Self {
        PREEMPTABLE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for PREEMPTABLE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PREEMPTABLE` writer - ?1?: Transfer is preemptable. In DMA mode (OPCODE is ?1? or ?2?), multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled."]
pub struct PREEMPTABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> PREEMPTABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
        self.w
    }
}
#[doc = "Field `FLIPPING` reader - ?1?: On completion of the current descriptor structure, the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures."]
pub struct FLIPPING_R(crate::FieldReader<bool, bool>);
impl FLIPPING_R {
    pub(crate) fn new(bits: bool) -> Self {
        FLIPPING_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for FLIPPING_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FLIPPING` writer - ?1?: On completion of the current descriptor structure, the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures."]
pub struct FLIPPING_W<'a> {
    w: &'a mut W,
}
impl<'a> FLIPPING_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
        self.w
    }
}
#[doc = "Field `OPCODE` reader - Specifies the specific data transfer (only when the VALID bit of the descriptor?s STATUS word is ?1?):???0?: A single trigger initiates a single data element transfer (DW mode). This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1).???1?: A single trigger initiates a single descriptor transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed.???2?: A single trigger initiates a descriptor list transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer).??After completerion of the opcode (and waiting for de-activation, the channel's output trigger is activated)."]
pub struct OPCODE_R(crate::FieldReader<u8, u8>);
impl OPCODE_R {
    pub(crate) fn new(bits: u8) -> Self {
        OPCODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for OPCODE_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `OPCODE` writer - Specifies the specific data transfer (only when the VALID bit of the descriptor?s STATUS word is ?1?):???0?: A single trigger initiates a single data element transfer (DW mode). This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1).???1?: A single trigger initiates a single descriptor transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed.???2?: A single trigger initiates a descriptor list transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer).??After completerion of the opcode (and waiting for de-activation, the channel's output trigger is activated)."]
pub struct OPCODE_W<'a> {
    w: &'a mut W,
}
impl<'a> OPCODE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:15 - Number of data elements that are transferred by a single descriptor.?In DW mode (OPCODE is ?0?) each trigger initiates the transfer of a single data element. This field specifies the source and/or destination buffer size in data elements: buffer size = DATA_NR+1. The buffer is typically associated to a memory structure.?In DMA mode (OPCODE is ?1? or ?2?) each trigger initiates the transfer of DATA_NR+1 data elements."]
    #[inline(always)]
    pub fn data_nr(&self) -> DATA_NR_R {
        DATA_NR_R::new((self.bits & 0xffff) as u16)
    }
    #[doc = "Bits 16:17 - Specifies the data element size:??0?: Byte (8 bits).??1?: Halfword (16 bits).??2?: Word (32 bits).?DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:?- DATA is 8 bit, SRC is 8 bit, DST is 8 bit?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit?- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 16 bit, SRC is 16 bit, DST is 16 bit?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit?- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 32 bit, SRC is 32 bit, DST is 32 bit"]
    #[inline(always)]
    pub fn data_size(&self) -> DATA_SIZE_R {
        DATA_SIZE_R::new(((self.bits >> 16) & 0x03) as u8)
    }
    #[doc = "Bit 20 - Specifies the bus transfer size to the destination location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element."]
    #[inline(always)]
    pub fn dst_transfer_size(&self) -> DST_TRANSFER_SIZE_R {
        DST_TRANSFER_SIZE_R::new(((self.bits >> 20) & 0x01) != 0)
    }
    #[doc = "Bit 21 - Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not.??0? : No increment, typically used for transmit (TX) FIFO structures.??1?: Increment, typically used for memory structures."]
    #[inline(always)]
    pub fn dst_addr_incr(&self) -> DST_ADDR_INCR_R {
        DST_ADDR_INCR_R::new(((self.bits >> 21) & 0x01) != 0)
    }
    #[doc = "Bit 22 - Specifies the bus transfer size to the source location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element."]
    #[inline(always)]
    pub fn src_transfer_size(&self) -> SRC_TRANSFER_SIZE_R {
        SRC_TRANSFER_SIZE_R::new(((self.bits >> 22) & 0x01) != 0)
    }
    #[doc = "Bit 23 - Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not.??0?: No increment, typically used for receive (RX) FIFO structures.??1?: Increment, typically used for memory structures."]
    #[inline(always)]
    pub fn src_addr_incr(&self) -> SRC_ADDR_INCR_R {
        SRC_ADDR_INCR_R::new(((self.bits >> 23) & 0x01) != 0)
    }
    #[doc = "Bits 24:25 - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller?s data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent?s trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to \"0\"). The wait cycles incurred by this field reduce DW/DMA controller performance.??0?: Do not wait for de-activation (for pulse sensitive triggers).??1?: Wait for up to 4 cycles.??2?: Wait for up to 8 cycles.??3?: Wait indefinitely. This option may result in DW/DMA controller lockup if the system trigger is not de-activated by the source agent."]
    #[inline(always)]
    pub fn wait_for_deact(&self) -> WAIT_FOR_DEACT_R {
        WAIT_FOR_DEACT_R::new(((self.bits >> 24) & 0x03) as u8)
    }
    #[doc = "Bit 26 - ?1?: On completion of the current descriptor structure, the VALID bit of the descriptor?s STATUS word is set to ?0?."]
    #[inline(always)]
    pub fn inv_descr(&self) -> INV_DESCR_R {
        INV_DESCR_R::new(((self.bits >> 26) & 0x01) != 0)
    }
    #[doc = "Bit 27 - ?1?: On completion of the current descriptor structure, the interrupt cause field of the channel is set to ?1? (INTR.CH\\[i\\])."]
    #[inline(always)]
    pub fn set_cause(&self) -> SET_CAUSE_R {
        SET_CAUSE_R::new(((self.bits >> 27) & 0x01) != 0)
    }
    #[doc = "Bit 28 - ?1?: Transfer is preemptable. In DMA mode (OPCODE is ?1? or ?2?), multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled."]
    #[inline(always)]
    pub fn preemptable(&self) -> PREEMPTABLE_R {
        PREEMPTABLE_R::new(((self.bits >> 28) & 0x01) != 0)
    }
    #[doc = "Bit 29 - ?1?: On completion of the current descriptor structure, the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures."]
    #[inline(always)]
    pub fn flipping(&self) -> FLIPPING_R {
        FLIPPING_R::new(((self.bits >> 29) & 0x01) != 0)
    }
    #[doc = "Bits 30:31 - Specifies the specific data transfer (only when the VALID bit of the descriptor?s STATUS word is ?1?):???0?: A single trigger initiates a single data element transfer (DW mode). This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1).???1?: A single trigger initiates a single descriptor transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed.???2?: A single trigger initiates a descriptor list transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer).??After completerion of the opcode (and waiting for de-activation, the channel's output trigger is activated)."]
    #[inline(always)]
    pub fn opcode(&self) -> OPCODE_R {
        OPCODE_R::new(((self.bits >> 30) & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bits 0:15 - Number of data elements that are transferred by a single descriptor.?In DW mode (OPCODE is ?0?) each trigger initiates the transfer of a single data element. This field specifies the source and/or destination buffer size in data elements: buffer size = DATA_NR+1. The buffer is typically associated to a memory structure.?In DMA mode (OPCODE is ?1? or ?2?) each trigger initiates the transfer of DATA_NR+1 data elements."]
    #[inline(always)]
    pub fn data_nr(&mut self) -> DATA_NR_W {
        DATA_NR_W { w: self }
    }
    #[doc = "Bits 16:17 - Specifies the data element size:??0?: Byte (8 bits).??1?: Halfword (16 bits).??2?: Word (32 bits).?DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:?- DATA is 8 bit, SRC is 8 bit, DST is 8 bit?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit?- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made ?0?)?- DATA is 16 bit, SRC is 16 bit, DST is 16 bit?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit?- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made ?0?)?- DATA is 32 bit, SRC is 32 bit, DST is 32 bit"]
    #[inline(always)]
    pub fn data_size(&mut self) -> DATA_SIZE_W {
        DATA_SIZE_W { w: self }
    }
    #[doc = "Bit 20 - Specifies the bus transfer size to the destination location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element."]
    #[inline(always)]
    pub fn dst_transfer_size(&mut self) -> DST_TRANSFER_SIZE_W {
        DST_TRANSFER_SIZE_W { w: self }
    }
    #[doc = "Bit 21 - Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not.??0? : No increment, typically used for transmit (TX) FIFO structures.??1?: Increment, typically used for memory structures."]
    #[inline(always)]
    pub fn dst_addr_incr(&mut self) -> DST_ADDR_INCR_W {
        DST_ADDR_INCR_W { w: self }
    }
    #[doc = "Bit 22 - Specifies the bus transfer size to the source location:??0?: As specified by DATA_SIZE.??1?: Word (32 bits).?Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element."]
    #[inline(always)]
    pub fn src_transfer_size(&mut self) -> SRC_TRANSFER_SIZE_W {
        SRC_TRANSFER_SIZE_W { w: self }
    }
    #[doc = "Bit 23 - Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not.??0?: No increment, typically used for receive (RX) FIFO structures.??1?: Increment, typically used for memory structures."]
    #[inline(always)]
    pub fn src_addr_incr(&mut self) -> SRC_ADDR_INCR_W {
        SRC_ADDR_INCR_W { w: self }
    }
    #[doc = "Bits 24:25 - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller?s data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent?s trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to \"0\"). The wait cycles incurred by this field reduce DW/DMA controller performance.??0?: Do not wait for de-activation (for pulse sensitive triggers).??1?: Wait for up to 4 cycles.??2?: Wait for up to 8 cycles.??3?: Wait indefinitely. This option may result in DW/DMA controller lockup if the system trigger is not de-activated by the source agent."]
    #[inline(always)]
    pub fn wait_for_deact(&mut self) -> WAIT_FOR_DEACT_W {
        WAIT_FOR_DEACT_W { w: self }
    }
    #[doc = "Bit 26 - ?1?: On completion of the current descriptor structure, the VALID bit of the descriptor?s STATUS word is set to ?0?."]
    #[inline(always)]
    pub fn inv_descr(&mut self) -> INV_DESCR_W {
        INV_DESCR_W { w: self }
    }
    #[doc = "Bit 27 - ?1?: On completion of the current descriptor structure, the interrupt cause field of the channel is set to ?1? (INTR.CH\\[i\\])."]
    #[inline(always)]
    pub fn set_cause(&mut self) -> SET_CAUSE_W {
        SET_CAUSE_W { w: self }
    }
    #[doc = "Bit 28 - ?1?: Transfer is preemptable. In DMA mode (OPCODE is ?1? or ?2?), multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled."]
    #[inline(always)]
    pub fn preemptable(&mut self) -> PREEMPTABLE_W {
        PREEMPTABLE_W { w: self }
    }
    #[doc = "Bit 29 - ?1?: On completion of the current descriptor structure, the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures."]
    #[inline(always)]
    pub fn flipping(&mut self) -> FLIPPING_W {
        FLIPPING_W { w: self }
    }
    #[doc = "Bits 30:31 - Specifies the specific data transfer (only when the VALID bit of the descriptor?s STATUS word is ?1?):???0?: A single trigger initiates a single data element transfer (DW mode). This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1).???1?: A single trigger initiates a single descriptor transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed.???2?: A single trigger initiates a descriptor list transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer).??After completerion of the opcode (and waiting for de-activation, the channel's output trigger is activated)."]
    #[inline(always)]
    pub fn opcode(&mut self) -> OPCODE_W {
        OPCODE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Ping control word\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ping_ctl](index.html) module"]
pub struct PING_CTL_SPEC;
impl crate::RegisterSpec for PING_CTL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [ping_ctl::R](R) reader structure"]
impl crate::Readable for PING_CTL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ping_ctl::W](W) writer structure"]
impl crate::Writable for PING_CTL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PING_CTL to value 0"]
impl crate::Resettable for PING_CTL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
