#[doc = "Register `QCLK_EN2` reader"]
pub struct R(crate::R<QCLK_EN2_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<QCLK_EN2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<QCLK_EN2_SPEC>> for R {
    fn from(reader: crate::R<QCLK_EN2_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `QCLK_EN2` writer"]
pub struct W(crate::W<QCLK_EN2_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<QCLK_EN2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<QCLK_EN2_SPEC>> for W {
    fn from(writer: crate::W<QCLK_EN2_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Digital clock enable for indexed digital clock for the associated quadrant.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DCEN_Q_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<DCEN_Q_A> for u8 {
    #[inline(always)]
    fn from(variant: DCEN_Q_A) -> Self {
        variant as _
    }
}
#[doc = "Field `DCEN_Q` reader - Digital clock enable for indexed digital clock for the associated quadrant."]
pub struct DCEN_Q_R(crate::FieldReader<u8, DCEN_Q_A>);
impl DCEN_Q_R {
    pub(crate) fn new(bits: u8) -> Self {
        DCEN_Q_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<DCEN_Q_A> {
        match self.bits {
            0 => Some(DCEN_Q_A::DISABLE),
            1 => Some(DCEN_Q_A::ENABLE),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == DCEN_Q_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == DCEN_Q_A::ENABLE
    }
}
impl core::ops::Deref for DCEN_Q_R {
    type Target = crate::FieldReader<u8, DCEN_Q_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DCEN_Q` writer - Digital clock enable for indexed digital clock for the associated quadrant."]
pub struct DCEN_Q_W<'a> {
    w: &'a mut W,
}
impl<'a> DCEN_Q_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DCEN_Q_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(DCEN_Q_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(DCEN_Q_A::ENABLE)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | (value as u16 & 0xff);
        self.w
    }
}
#[doc = "Bank Clock Enable Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BCEN_Q_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<BCEN_Q_A> for bool {
    #[inline(always)]
    fn from(variant: BCEN_Q_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `BCEN_Q` reader - Bank Clock Enable Control"]
pub struct BCEN_Q_R(crate::FieldReader<bool, BCEN_Q_A>);
impl BCEN_Q_R {
    pub(crate) fn new(bits: bool) -> Self {
        BCEN_Q_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> BCEN_Q_A {
        match self.bits {
            false => BCEN_Q_A::DISABLE,
            true => BCEN_Q_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == BCEN_Q_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == BCEN_Q_A::ENABLE
    }
}
impl core::ops::Deref for BCEN_Q_R {
    type Target = crate::FieldReader<bool, BCEN_Q_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `BCEN_Q` writer - Bank Clock Enable Control"]
pub struct BCEN_Q_W<'a> {
    w: &'a mut W,
}
impl<'a> BCEN_Q_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: BCEN_Q_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(BCEN_Q_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(BCEN_Q_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8);
        self.w
    }
}
#[doc = "Enable global write operation for the routing channel with the lower address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GCH_WR_LO_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<GCH_WR_LO_A> for bool {
    #[inline(always)]
    fn from(variant: GCH_WR_LO_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `GCH_WR_LO` reader - Enable global write operation for the routing channel with the lower address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
pub struct GCH_WR_LO_R(crate::FieldReader<bool, GCH_WR_LO_A>);
impl GCH_WR_LO_R {
    pub(crate) fn new(bits: bool) -> Self {
        GCH_WR_LO_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> GCH_WR_LO_A {
        match self.bits {
            false => GCH_WR_LO_A::DISABLE,
            true => GCH_WR_LO_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == GCH_WR_LO_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == GCH_WR_LO_A::ENABLE
    }
}
impl core::ops::Deref for GCH_WR_LO_R {
    type Target = crate::FieldReader<bool, GCH_WR_LO_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `GCH_WR_LO` writer - Enable global write operation for the routing channel with the lower address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
pub struct GCH_WR_LO_W<'a> {
    w: &'a mut W,
}
impl<'a> GCH_WR_LO_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: GCH_WR_LO_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(GCH_WR_LO_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(GCH_WR_LO_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9);
        self.w
    }
}
#[doc = "Enable global write operation for the routing channel with the higher address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GCH_WR_HI_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<GCH_WR_HI_A> for bool {
    #[inline(always)]
    fn from(variant: GCH_WR_HI_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `GCH_WR_HI` reader - Enable global write operation for the routing channel with the higher address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
pub struct GCH_WR_HI_R(crate::FieldReader<bool, GCH_WR_HI_A>);
impl GCH_WR_HI_R {
    pub(crate) fn new(bits: bool) -> Self {
        GCH_WR_HI_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> GCH_WR_HI_A {
        match self.bits {
            false => GCH_WR_HI_A::DISABLE,
            true => GCH_WR_HI_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == GCH_WR_HI_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == GCH_WR_HI_A::ENABLE
    }
}
impl core::ops::Deref for GCH_WR_HI_R {
    type Target = crate::FieldReader<bool, GCH_WR_HI_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `GCH_WR_HI` writer - Enable global write operation for the routing channel with the higher address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
pub struct GCH_WR_HI_W<'a> {
    w: &'a mut W,
}
impl<'a> GCH_WR_HI_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: GCH_WR_HI_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(GCH_WR_HI_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(GCH_WR_HI_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10);
        self.w
    }
}
#[doc = "By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DISABLE_ROUTE_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<DISABLE_ROUTE_A> for bool {
    #[inline(always)]
    fn from(variant: DISABLE_ROUTE_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `DISABLE_ROUTE` reader - By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit."]
pub struct DISABLE_ROUTE_R(crate::FieldReader<bool, DISABLE_ROUTE_A>);
impl DISABLE_ROUTE_R {
    pub(crate) fn new(bits: bool) -> Self {
        DISABLE_ROUTE_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> DISABLE_ROUTE_A {
        match self.bits {
            false => DISABLE_ROUTE_A::DISABLE,
            true => DISABLE_ROUTE_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == DISABLE_ROUTE_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == DISABLE_ROUTE_A::ENABLE
    }
}
impl core::ops::Deref for DISABLE_ROUTE_R {
    type Target = crate::FieldReader<bool, DISABLE_ROUTE_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DISABLE_ROUTE` writer - By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit."]
pub struct DISABLE_ROUTE_W<'a> {
    w: &'a mut W,
}
impl<'a> DISABLE_ROUTE_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: DISABLE_ROUTE_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(DISABLE_ROUTE_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(DISABLE_ROUTE_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11);
        self.w
    }
}
#[doc = "Enable global write operation for the DSI routing channels. When this bit is set, the DSI ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls upper half DSI blocks. The GLB_DSI_WR bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GLB_DSI_WR_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<GLB_DSI_WR_A> for bool {
    #[inline(always)]
    fn from(variant: GLB_DSI_WR_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `GLB_DSI_WR` reader - Enable global write operation for the DSI routing channels. When this bit is set, the DSI ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls upper half DSI blocks. The GLB_DSI_WR bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
pub struct GLB_DSI_WR_R(crate::FieldReader<bool, GLB_DSI_WR_A>);
impl GLB_DSI_WR_R {
    pub(crate) fn new(bits: bool) -> Self {
        GLB_DSI_WR_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> GLB_DSI_WR_A {
        match self.bits {
            false => GLB_DSI_WR_A::DISABLE,
            true => GLB_DSI_WR_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == GLB_DSI_WR_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == GLB_DSI_WR_A::ENABLE
    }
}
impl core::ops::Deref for GLB_DSI_WR_R {
    type Target = crate::FieldReader<bool, GLB_DSI_WR_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `GLB_DSI_WR` writer - Enable global write operation for the DSI routing channels. When this bit is set, the DSI ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls upper half DSI blocks. The GLB_DSI_WR bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
pub struct GLB_DSI_WR_W<'a> {
    w: &'a mut W,
}
impl<'a> GLB_DSI_WR_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: GLB_DSI_WR_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(GLB_DSI_WR_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(GLB_DSI_WR_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12);
        self.w
    }
}
#[doc = "Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB. Only one QCLK_ENx register per bank has an active bit. BCTL0_QCLK_EN0\\[15:8\\]
controls this bit for Bank 0. The WR_CFG_OPT bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WR_CFG_OPT_A {
    #[doc = "0: No description available"]
    FULL_CYCLE_STB = 0,
    #[doc = "1: No description available"]
    HALF_CYCLE_STB = 1,
}
impl From<WR_CFG_OPT_A> for bool {
    #[inline(always)]
    fn from(variant: WR_CFG_OPT_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `WR_CFG_OPT` reader - Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB. Only one QCLK_ENx register per bank has an active bit. BCTL0_QCLK_EN0\\[15:8\\]
controls this bit for Bank 0. The WR_CFG_OPT bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
pub struct WR_CFG_OPT_R(crate::FieldReader<bool, WR_CFG_OPT_A>);
impl WR_CFG_OPT_R {
    pub(crate) fn new(bits: bool) -> Self {
        WR_CFG_OPT_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> WR_CFG_OPT_A {
        match self.bits {
            false => WR_CFG_OPT_A::FULL_CYCLE_STB,
            true => WR_CFG_OPT_A::HALF_CYCLE_STB,
        }
    }
    #[doc = "Checks if the value of the field is `FULL_CYCLE_STB`"]
    #[inline(always)]
    pub fn is_full_cycle_stb(&self) -> bool {
        **self == WR_CFG_OPT_A::FULL_CYCLE_STB
    }
    #[doc = "Checks if the value of the field is `HALF_CYCLE_STB`"]
    #[inline(always)]
    pub fn is_half_cycle_stb(&self) -> bool {
        **self == WR_CFG_OPT_A::HALF_CYCLE_STB
    }
}
impl core::ops::Deref for WR_CFG_OPT_R {
    type Target = crate::FieldReader<bool, WR_CFG_OPT_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `WR_CFG_OPT` writer - Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB. Only one QCLK_ENx register per bank has an active bit. BCTL0_QCLK_EN0\\[15:8\\]
controls this bit for Bank 0. The WR_CFG_OPT bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
pub struct WR_CFG_OPT_W<'a> {
    w: &'a mut W,
}
impl<'a> WR_CFG_OPT_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: WR_CFG_OPT_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn full_cycle_stb(self) -> &'a mut W {
        self.variant(WR_CFG_OPT_A::FULL_CYCLE_STB)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn half_cycle_stb(self) -> &'a mut W {
        self.variant(WR_CFG_OPT_A::HALF_CYCLE_STB)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13);
        self.w
    }
}
#[doc = "Field `NC0` reader - Spare register bit"]
pub struct NC0_R(crate::FieldReader<bool, bool>);
impl NC0_R {
    pub(crate) fn new(bits: bool) -> Self {
        NC0_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for NC0_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `NC0` writer - Spare register bit"]
pub struct NC0_W<'a> {
    w: &'a mut W,
}
impl<'a> NC0_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14);
        self.w
    }
}
#[doc = "Assertion of this bit drives sleep into the UDB array for internal UDB test purposes. Assertion does not affect the power switches. This signal drives pulldowns on the write strobes for all configuration memory, inhibiting writes when set. Sleep or sleep_test does not inhibit writes to this bit, allowing it to be cleared once it has been set. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls Bank 0 UDB pairs 0-3 and lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls Bank 0 UDB pairs 4-7 and upper half DSI blocks.? The SLEEP_TEST bits in the other BCTLx_QCLK_ENy registers are not used. Sleep assertion drives bus_rdata to zero so bus read transactions will not return data during assertion of certain sleep_test bits. This is only true for assertion of sleep_test in BCTL0_QCLK_EN0 for Bank 0.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SLEEP_TEST_A {
    #[doc = "0: No description available"]
    DISABLE = 0,
    #[doc = "1: No description available"]
    ENABLE = 1,
}
impl From<SLEEP_TEST_A> for bool {
    #[inline(always)]
    fn from(variant: SLEEP_TEST_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `SLEEP_TEST` reader - Assertion of this bit drives sleep into the UDB array for internal UDB test purposes. Assertion does not affect the power switches. This signal drives pulldowns on the write strobes for all configuration memory, inhibiting writes when set. Sleep or sleep_test does not inhibit writes to this bit, allowing it to be cleared once it has been set. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls Bank 0 UDB pairs 0-3 and lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls Bank 0 UDB pairs 4-7 and upper half DSI blocks.? The SLEEP_TEST bits in the other BCTLx_QCLK_ENy registers are not used. Sleep assertion drives bus_rdata to zero so bus read transactions will not return data during assertion of certain sleep_test bits. This is only true for assertion of sleep_test in BCTL0_QCLK_EN0 for Bank 0."]
pub struct SLEEP_TEST_R(crate::FieldReader<bool, SLEEP_TEST_A>);
impl SLEEP_TEST_R {
    pub(crate) fn new(bits: bool) -> Self {
        SLEEP_TEST_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SLEEP_TEST_A {
        match self.bits {
            false => SLEEP_TEST_A::DISABLE,
            true => SLEEP_TEST_A::ENABLE,
        }
    }
    #[doc = "Checks if the value of the field is `DISABLE`"]
    #[inline(always)]
    pub fn is_disable(&self) -> bool {
        **self == SLEEP_TEST_A::DISABLE
    }
    #[doc = "Checks if the value of the field is `ENABLE`"]
    #[inline(always)]
    pub fn is_enable(&self) -> bool {
        **self == SLEEP_TEST_A::ENABLE
    }
}
impl core::ops::Deref for SLEEP_TEST_R {
    type Target = crate::FieldReader<bool, SLEEP_TEST_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SLEEP_TEST` writer - Assertion of this bit drives sleep into the UDB array for internal UDB test purposes. Assertion does not affect the power switches. This signal drives pulldowns on the write strobes for all configuration memory, inhibiting writes when set. Sleep or sleep_test does not inhibit writes to this bit, allowing it to be cleared once it has been set. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls Bank 0 UDB pairs 0-3 and lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls Bank 0 UDB pairs 4-7 and upper half DSI blocks.? The SLEEP_TEST bits in the other BCTLx_QCLK_ENy registers are not used. Sleep assertion drives bus_rdata to zero so bus read transactions will not return data during assertion of certain sleep_test bits. This is only true for assertion of sleep_test in BCTL0_QCLK_EN0 for Bank 0."]
pub struct SLEEP_TEST_W<'a> {
    w: &'a mut W,
}
impl<'a> SLEEP_TEST_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SLEEP_TEST_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn disable(self) -> &'a mut W {
        self.variant(SLEEP_TEST_A::DISABLE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn enable(self) -> &'a mut W {
        self.variant(SLEEP_TEST_A::ENABLE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:7 - Digital clock enable for indexed digital clock for the associated quadrant."]
    #[inline(always)]
    pub fn dcen_q(&self) -> DCEN_Q_R {
        DCEN_Q_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bit 8 - Bank Clock Enable Control"]
    #[inline(always)]
    pub fn bcen_q(&self) -> BCEN_Q_R {
        BCEN_Q_R::new(((self.bits >> 8) & 0x01) != 0)
    }
    #[doc = "Bit 9 - Enable global write operation for the routing channel with the lower address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
    #[inline(always)]
    pub fn gch_wr_lo(&self) -> GCH_WR_LO_R {
        GCH_WR_LO_R::new(((self.bits >> 9) & 0x01) != 0)
    }
    #[doc = "Bit 10 - Enable global write operation for the routing channel with the higher address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
    #[inline(always)]
    pub fn gch_wr_hi(&self) -> GCH_WR_HI_R {
        GCH_WR_HI_R::new(((self.bits >> 10) & 0x01) != 0)
    }
    #[doc = "Bit 11 - By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit."]
    #[inline(always)]
    pub fn disable_route(&self) -> DISABLE_ROUTE_R {
        DISABLE_ROUTE_R::new(((self.bits >> 11) & 0x01) != 0)
    }
    #[doc = "Bit 12 - Enable global write operation for the DSI routing channels. When this bit is set, the DSI ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls upper half DSI blocks. The GLB_DSI_WR bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
    #[inline(always)]
    pub fn glb_dsi_wr(&self) -> GLB_DSI_WR_R {
        GLB_DSI_WR_R::new(((self.bits >> 12) & 0x01) != 0)
    }
    #[doc = "Bit 13 - Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB. Only one QCLK_ENx register per bank has an active bit. BCTL0_QCLK_EN0\\[15:8\\]
controls this bit for Bank 0. The WR_CFG_OPT bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
    #[inline(always)]
    pub fn wr_cfg_opt(&self) -> WR_CFG_OPT_R {
        WR_CFG_OPT_R::new(((self.bits >> 13) & 0x01) != 0)
    }
    #[doc = "Bit 14 - Spare register bit"]
    #[inline(always)]
    pub fn nc0(&self) -> NC0_R {
        NC0_R::new(((self.bits >> 14) & 0x01) != 0)
    }
    #[doc = "Bit 15 - Assertion of this bit drives sleep into the UDB array for internal UDB test purposes. Assertion does not affect the power switches. This signal drives pulldowns on the write strobes for all configuration memory, inhibiting writes when set. Sleep or sleep_test does not inhibit writes to this bit, allowing it to be cleared once it has been set. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls Bank 0 UDB pairs 0-3 and lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls Bank 0 UDB pairs 4-7 and upper half DSI blocks.? The SLEEP_TEST bits in the other BCTLx_QCLK_ENy registers are not used. Sleep assertion drives bus_rdata to zero so bus read transactions will not return data during assertion of certain sleep_test bits. This is only true for assertion of sleep_test in BCTL0_QCLK_EN0 for Bank 0."]
    #[inline(always)]
    pub fn sleep_test(&self) -> SLEEP_TEST_R {
        SLEEP_TEST_R::new(((self.bits >> 15) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:7 - Digital clock enable for indexed digital clock for the associated quadrant."]
    #[inline(always)]
    pub fn dcen_q(&mut self) -> DCEN_Q_W {
        DCEN_Q_W { w: self }
    }
    #[doc = "Bit 8 - Bank Clock Enable Control"]
    #[inline(always)]
    pub fn bcen_q(&mut self) -> BCEN_Q_W {
        BCEN_Q_W { w: self }
    }
    #[doc = "Bit 9 - Enable global write operation for the routing channel with the lower address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
    #[inline(always)]
    pub fn gch_wr_lo(&mut self) -> GCH_WR_LO_W {
        GCH_WR_LO_W { w: self }
    }
    #[doc = "Bit 10 - Enable global write operation for the routing channel with the higher address in the associated quadrant. When enabled, the UDB ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes."]
    #[inline(always)]
    pub fn gch_wr_hi(&mut self) -> GCH_WR_HI_W {
        GCH_WR_HI_W { w: self }
    }
    #[doc = "Bit 11 - By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit."]
    #[inline(always)]
    pub fn disable_route(&mut self) -> DISABLE_ROUTE_W {
        DISABLE_ROUTE_W { w: self }
    }
    #[doc = "Bit 12 - Enable global write operation for the DSI routing channels. When this bit is set, the DSI ID select decoding is bypassed and therefore multiple channels can be written to simultaneously. This is designed to support test modes. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls upper half DSI blocks. The GLB_DSI_WR bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
    #[inline(always)]
    pub fn glb_dsi_wr(&mut self) -> GLB_DSI_WR_W {
        GLB_DSI_WR_W { w: self }
    }
    #[doc = "Bit 13 - Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB. Only one QCLK_ENx register per bank has an active bit. BCTL0_QCLK_EN0\\[15:8\\]
controls this bit for Bank 0. The WR_CFG_OPT bits in the other BCTLx_QCLK_ENy\\[15:8\\]
registers are not used."]
    #[inline(always)]
    pub fn wr_cfg_opt(&mut self) -> WR_CFG_OPT_W {
        WR_CFG_OPT_W { w: self }
    }
    #[doc = "Bit 14 - Spare register bit"]
    #[inline(always)]
    pub fn nc0(&mut self) -> NC0_W {
        NC0_W { w: self }
    }
    #[doc = "Bit 15 - Assertion of this bit drives sleep into the UDB array for internal UDB test purposes. Assertion does not affect the power switches. This signal drives pulldowns on the write strobes for all configuration memory, inhibiting writes when set. Sleep or sleep_test does not inhibit writes to this bit, allowing it to be cleared once it has been set. Control is split top and bottom. BCTL0_QCLK_EN0\\[15:8\\]
controls Bank 0 UDB pairs 0-3 and lower half DSI blocks. BCTL0_QCLK_EN3\\[15:8\\]
controls Bank 0 UDB pairs 4-7 and upper half DSI blocks.? The SLEEP_TEST bits in the other BCTLx_QCLK_ENy registers are not used. Sleep assertion drives bus_rdata to zero so bus read transactions will not return data during assertion of certain sleep_test bits. This is only true for assertion of sleep_test in BCTL0_QCLK_EN0 for Bank 0."]
    #[inline(always)]
    pub fn sleep_test(&mut self) -> SLEEP_TEST_W {
        SLEEP_TEST_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Quadrant Digital Clock Enable Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qclk_en2](index.html) module"]
pub struct QCLK_EN2_SPEC;
impl crate::RegisterSpec for QCLK_EN2_SPEC {
    type Ux = u16;
}
#[doc = "`read()` method returns [qclk_en2::R](R) reader structure"]
impl crate::Readable for QCLK_EN2_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [qclk_en2::W](W) writer structure"]
impl crate::Writable for QCLK_EN2_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets QCLK_EN2 to value 0"]
impl crate::Resettable for QCLK_EN2_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
