#[doc = "Register `CFG28` reader"]
pub struct R(crate::R<CFG28_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG28_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG28_SPEC>> for R {
    fn from(reader: crate::R<CFG28_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG28` writer"]
pub struct W(crate::W<CFG28_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG28_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG28_SPEC>> for W {
    fn from(writer: crate::W<CFG28_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Clock selection registers\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum PLD0_CK_SEL_A {
    #[doc = "0: No description available"]
    GCLK0 = 0,
    #[doc = "1: No description available"]
    GCLK1 = 1,
    #[doc = "2: No description available"]
    GCLK2 = 2,
    #[doc = "3: No description available"]
    GCLK3 = 3,
    #[doc = "4: No description available"]
    GCLK4 = 4,
    #[doc = "5: No description available"]
    GCLK5 = 5,
    #[doc = "6: No description available"]
    GCLK6 = 6,
    #[doc = "7: No description available"]
    GCLK7 = 7,
    #[doc = "8: No description available"]
    EXT_CLK = 8,
    #[doc = "9: No description available"]
    SYSCLK = 9,
}
impl From<PLD0_CK_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: PLD0_CK_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `PLD0_CK_SEL` reader - Clock selection registers"]
pub struct PLD0_CK_SEL_R(crate::FieldReader<u8, PLD0_CK_SEL_A>);
impl PLD0_CK_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        PLD0_CK_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<PLD0_CK_SEL_A> {
        match self.bits {
            0 => Some(PLD0_CK_SEL_A::GCLK0),
            1 => Some(PLD0_CK_SEL_A::GCLK1),
            2 => Some(PLD0_CK_SEL_A::GCLK2),
            3 => Some(PLD0_CK_SEL_A::GCLK3),
            4 => Some(PLD0_CK_SEL_A::GCLK4),
            5 => Some(PLD0_CK_SEL_A::GCLK5),
            6 => Some(PLD0_CK_SEL_A::GCLK6),
            7 => Some(PLD0_CK_SEL_A::GCLK7),
            8 => Some(PLD0_CK_SEL_A::EXT_CLK),
            9 => Some(PLD0_CK_SEL_A::SYSCLK),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `GCLK0`"]
    #[inline(always)]
    pub fn is_gclk0(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK0
    }
    #[doc = "Checks if the value of the field is `GCLK1`"]
    #[inline(always)]
    pub fn is_gclk1(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK1
    }
    #[doc = "Checks if the value of the field is `GCLK2`"]
    #[inline(always)]
    pub fn is_gclk2(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK2
    }
    #[doc = "Checks if the value of the field is `GCLK3`"]
    #[inline(always)]
    pub fn is_gclk3(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK3
    }
    #[doc = "Checks if the value of the field is `GCLK4`"]
    #[inline(always)]
    pub fn is_gclk4(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK4
    }
    #[doc = "Checks if the value of the field is `GCLK5`"]
    #[inline(always)]
    pub fn is_gclk5(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK5
    }
    #[doc = "Checks if the value of the field is `GCLK6`"]
    #[inline(always)]
    pub fn is_gclk6(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK6
    }
    #[doc = "Checks if the value of the field is `GCLK7`"]
    #[inline(always)]
    pub fn is_gclk7(&self) -> bool {
        **self == PLD0_CK_SEL_A::GCLK7
    }
    #[doc = "Checks if the value of the field is `EXT_CLK`"]
    #[inline(always)]
    pub fn is_ext_clk(&self) -> bool {
        **self == PLD0_CK_SEL_A::EXT_CLK
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline(always)]
    pub fn is_sysclk(&self) -> bool {
        **self == PLD0_CK_SEL_A::SYSCLK
    }
}
impl core::ops::Deref for PLD0_CK_SEL_R {
    type Target = crate::FieldReader<u8, PLD0_CK_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PLD0_CK_SEL` writer - Clock selection registers"]
pub struct PLD0_CK_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> PLD0_CK_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLD0_CK_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk0(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk1(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk2(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk3(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK3)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk4(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK4)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk5(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK5)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk6(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK6)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk7(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::GCLK7)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn ext_clk(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::EXT_CLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(PLD0_CK_SEL_A::SYSCLK)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f);
        self.w
    }
}
#[doc = "Clock selection registers\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum PLD1_CK_SEL_A {
    #[doc = "0: No description available"]
    GCLK0 = 0,
    #[doc = "1: No description available"]
    GCLK1 = 1,
    #[doc = "2: No description available"]
    GCLK2 = 2,
    #[doc = "3: No description available"]
    GCLK3 = 3,
    #[doc = "4: No description available"]
    GCLK4 = 4,
    #[doc = "5: No description available"]
    GCLK5 = 5,
    #[doc = "6: No description available"]
    GCLK6 = 6,
    #[doc = "7: No description available"]
    GCLK7 = 7,
    #[doc = "8: No description available"]
    EXT_CLK = 8,
    #[doc = "9: No description available"]
    SYSCLK = 9,
}
impl From<PLD1_CK_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: PLD1_CK_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `PLD1_CK_SEL` reader - Clock selection registers"]
pub struct PLD1_CK_SEL_R(crate::FieldReader<u8, PLD1_CK_SEL_A>);
impl PLD1_CK_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        PLD1_CK_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<PLD1_CK_SEL_A> {
        match self.bits {
            0 => Some(PLD1_CK_SEL_A::GCLK0),
            1 => Some(PLD1_CK_SEL_A::GCLK1),
            2 => Some(PLD1_CK_SEL_A::GCLK2),
            3 => Some(PLD1_CK_SEL_A::GCLK3),
            4 => Some(PLD1_CK_SEL_A::GCLK4),
            5 => Some(PLD1_CK_SEL_A::GCLK5),
            6 => Some(PLD1_CK_SEL_A::GCLK6),
            7 => Some(PLD1_CK_SEL_A::GCLK7),
            8 => Some(PLD1_CK_SEL_A::EXT_CLK),
            9 => Some(PLD1_CK_SEL_A::SYSCLK),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `GCLK0`"]
    #[inline(always)]
    pub fn is_gclk0(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK0
    }
    #[doc = "Checks if the value of the field is `GCLK1`"]
    #[inline(always)]
    pub fn is_gclk1(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK1
    }
    #[doc = "Checks if the value of the field is `GCLK2`"]
    #[inline(always)]
    pub fn is_gclk2(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK2
    }
    #[doc = "Checks if the value of the field is `GCLK3`"]
    #[inline(always)]
    pub fn is_gclk3(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK3
    }
    #[doc = "Checks if the value of the field is `GCLK4`"]
    #[inline(always)]
    pub fn is_gclk4(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK4
    }
    #[doc = "Checks if the value of the field is `GCLK5`"]
    #[inline(always)]
    pub fn is_gclk5(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK5
    }
    #[doc = "Checks if the value of the field is `GCLK6`"]
    #[inline(always)]
    pub fn is_gclk6(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK6
    }
    #[doc = "Checks if the value of the field is `GCLK7`"]
    #[inline(always)]
    pub fn is_gclk7(&self) -> bool {
        **self == PLD1_CK_SEL_A::GCLK7
    }
    #[doc = "Checks if the value of the field is `EXT_CLK`"]
    #[inline(always)]
    pub fn is_ext_clk(&self) -> bool {
        **self == PLD1_CK_SEL_A::EXT_CLK
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline(always)]
    pub fn is_sysclk(&self) -> bool {
        **self == PLD1_CK_SEL_A::SYSCLK
    }
}
impl core::ops::Deref for PLD1_CK_SEL_R {
    type Target = crate::FieldReader<u8, PLD1_CK_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PLD1_CK_SEL` writer - Clock selection registers"]
pub struct PLD1_CK_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> PLD1_CK_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLD1_CK_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk0(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk1(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk2(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk3(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK3)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk4(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK4)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk5(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK5)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk6(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK6)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gclk7(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::GCLK7)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn ext_clk(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::EXT_CLK)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(PLD1_CK_SEL_A::SYSCLK)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:3 - Clock selection registers"]
    #[inline(always)]
    pub fn pld0_ck_sel(&self) -> PLD0_CK_SEL_R {
        PLD0_CK_SEL_R::new((self.bits & 0x0f) as u8)
    }
    #[doc = "Bits 4:7 - Clock selection registers"]
    #[inline(always)]
    pub fn pld1_ck_sel(&self) -> PLD1_CK_SEL_R {
        PLD1_CK_SEL_R::new(((self.bits >> 4) & 0x0f) as u8)
    }
}
impl W {
    #[doc = "Bits 0:3 - Clock selection registers"]
    #[inline(always)]
    pub fn pld0_ck_sel(&mut self) -> PLD0_CK_SEL_W {
        PLD0_CK_SEL_W { w: self }
    }
    #[doc = "Bits 4:7 - Clock selection registers"]
    #[inline(always)]
    pub fn pld1_ck_sel(&mut self) -> PLD1_CK_SEL_W {
        PLD1_CK_SEL_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Clock Selection for PLD1 and PLD0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg28](index.html) module"]
pub struct CFG28_SPEC;
impl crate::RegisterSpec for CFG28_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg28::R](R) reader structure"]
impl crate::Readable for CFG28_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg28::W](W) writer structure"]
impl crate::Writable for CFG28_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG28 to value 0"]
impl crate::Resettable for CFG28_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
