#[doc = "Register `PWR_CONTROL` reader"]
pub struct R(crate::R<PWR_CONTROL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PWR_CONTROL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<PWR_CONTROL_SPEC>> for R {
    fn from(reader: crate::R<PWR_CONTROL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PWR_CONTROL` writer"]
pub struct W(crate::W<PWR_CONTROL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PWR_CONTROL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<PWR_CONTROL_SPEC>> for W {
    fn from(writer: crate::W<PWR_CONTROL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum POWER_MODE_A {
    #[doc = "0: No description available"]
    RESET = 0,
    #[doc = "1: No description available"]
    ACTIVE = 1,
    #[doc = "2: No description available"]
    SLEEP = 2,
    #[doc = "3: No description available"]
    DEEP_SLEEP = 3,
    #[doc = "4: No description available"]
    HIBERNATE = 4,
}
impl From<POWER_MODE_A> for u8 {
    #[inline(always)]
    fn from(variant: POWER_MODE_A) -> Self {
        variant as _
    }
}
#[doc = "Field `POWER_MODE` reader - Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."]
pub struct POWER_MODE_R(crate::FieldReader<u8, POWER_MODE_A>);
impl POWER_MODE_R {
    pub(crate) fn new(bits: u8) -> Self {
        POWER_MODE_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<POWER_MODE_A> {
        match self.bits {
            0 => Some(POWER_MODE_A::RESET),
            1 => Some(POWER_MODE_A::ACTIVE),
            2 => Some(POWER_MODE_A::SLEEP),
            3 => Some(POWER_MODE_A::DEEP_SLEEP),
            4 => Some(POWER_MODE_A::HIBERNATE),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `RESET`"]
    #[inline(always)]
    pub fn is_reset(&self) -> bool {
        **self == POWER_MODE_A::RESET
    }
    #[doc = "Checks if the value of the field is `ACTIVE`"]
    #[inline(always)]
    pub fn is_active(&self) -> bool {
        **self == POWER_MODE_A::ACTIVE
    }
    #[doc = "Checks if the value of the field is `SLEEP`"]
    #[inline(always)]
    pub fn is_sleep(&self) -> bool {
        **self == POWER_MODE_A::SLEEP
    }
    #[doc = "Checks if the value of the field is `DEEP_SLEEP`"]
    #[inline(always)]
    pub fn is_deep_sleep(&self) -> bool {
        **self == POWER_MODE_A::DEEP_SLEEP
    }
    #[doc = "Checks if the value of the field is `HIBERNATE`"]
    #[inline(always)]
    pub fn is_hibernate(&self) -> bool {
        **self == POWER_MODE_A::HIBERNATE
    }
}
impl core::ops::Deref for POWER_MODE_R {
    type Target = crate::FieldReader<u8, POWER_MODE_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DEBUG_SESSION_A {
    #[doc = "0: No description available"]
    NO_SESSION = 0,
    #[doc = "1: No description available"]
    SESSION_ACTIVE = 1,
}
impl From<DEBUG_SESSION_A> for bool {
    #[inline(always)]
    fn from(variant: DEBUG_SESSION_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `DEBUG_SESSION` reader - Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)"]
pub struct DEBUG_SESSION_R(crate::FieldReader<bool, DEBUG_SESSION_A>);
impl DEBUG_SESSION_R {
    pub(crate) fn new(bits: bool) -> Self {
        DEBUG_SESSION_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> DEBUG_SESSION_A {
        match self.bits {
            false => DEBUG_SESSION_A::NO_SESSION,
            true => DEBUG_SESSION_A::SESSION_ACTIVE,
        }
    }
    #[doc = "Checks if the value of the field is `NO_SESSION`"]
    #[inline(always)]
    pub fn is_no_session(&self) -> bool {
        **self == DEBUG_SESSION_A::NO_SESSION
    }
    #[doc = "Checks if the value of the field is `SESSION_ACTIVE`"]
    #[inline(always)]
    pub fn is_session_active(&self) -> bool {
        **self == DEBUG_SESSION_A::SESSION_ACTIVE
    }
}
impl core::ops::Deref for DEBUG_SESSION_R {
    type Target = crate::FieldReader<bool, DEBUG_SESSION_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LPM_READY` reader - Indicates whether the low power mode regulators are ready to enter DEEPSLEEP or HIBERNATE mode. ?0: If DEEPSLEEP or HIBERNATE mode is requested, device will enter SLEEP mode. When low power regulators are ready, device will automatically enter the originally requested mode.?1: Normal operation. DEEPSLEEP and HIBERNATE work as described."]
pub struct LPM_READY_R(crate::FieldReader<bool, bool>);
impl LPM_READY_R {
    pub(crate) fn new(bits: bool) -> Self {
        LPM_READY_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for LPM_READY_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EXT_VCCD` reader - Should be set by firmware if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally."]
pub struct EXT_VCCD_R(crate::FieldReader<bool, bool>);
impl EXT_VCCD_R {
    pub(crate) fn new(bits: bool) -> Self {
        EXT_VCCD_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EXT_VCCD_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EXT_VCCD` writer - Should be set by firmware if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally."]
pub struct EXT_VCCD_W<'a> {
    w: &'a mut W,
}
impl<'a> EXT_VCCD_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
        self.w
    }
}
#[doc = "Field `HVMON_ENABLE` reader - 0: HV State Monitoring is disabled?1: HV State Monitoring is automatically enable by sleep controller"]
pub struct HVMON_ENABLE_R(crate::FieldReader<bool, bool>);
impl HVMON_ENABLE_R {
    pub(crate) fn new(bits: bool) -> Self {
        HVMON_ENABLE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for HVMON_ENABLE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HVMON_ENABLE` writer - 0: HV State Monitoring is disabled?1: HV State Monitoring is automatically enable by sleep controller"]
pub struct HVMON_ENABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> HVMON_ENABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
        self.w
    }
}
#[doc = "Field `HVMON_RELOAD` writer - Firmware writes 1 to reload HV State in hibernate shadow copy. Hardware clears this bit after reload was successful. Wait at least 9 cycles after writing/recalling NVL before reloading the HVMON."]
pub struct HVMON_RELOAD_W<'a> {
    w: &'a mut W,
}
impl<'a> HVMON_RELOAD_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
        self.w
    }
}
#[doc = "Field `FIMO_DISABLE` reader - This bit is asserted during the boot process?0: Forces IMO to operate at 12MHz, ignore its frequency and trim settings and operate independent on its external references.?1: Turns IMO into normal operational mode"]
pub struct FIMO_DISABLE_R(crate::FieldReader<bool, bool>);
impl FIMO_DISABLE_R {
    pub(crate) fn new(bits: bool) -> Self {
        FIMO_DISABLE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for FIMO_DISABLE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FIMO_DISABLE` writer - This bit is asserted during the boot process?0: Forces IMO to operate at 12MHz, ignore its frequency and trim settings and operate independent on its external references.?1: Turns IMO into normal operational mode"]
pub struct FIMO_DISABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> FIMO_DISABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
        self.w
    }
}
#[doc = "Field `HIBERNATE_DISABLE` writer - 0: Normal operation, HIBERNATE works as described?1: HIBERNATE bit is ignored, Hibernate mode is permanently disabled (part will go to DeepSleep instead.?Note: This bit is a write-once bit until the next reset."]
pub struct HIBERNATE_DISABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> HIBERNATE_DISABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
        self.w
    }
}
#[doc = "Field `LFCLK_SHORT` reader - Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode. This mode selection affects the accuracy specifications of the ILO oscillator due to supply noise. See Data Sheet for more details.?0: Do not short power domains?1: Short power domains"]
pub struct LFCLK_SHORT_R(crate::FieldReader<bool, bool>);
impl LFCLK_SHORT_R {
    pub(crate) fn new(bits: bool) -> Self {
        LFCLK_SHORT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for LFCLK_SHORT_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `LFCLK_SHORT` writer - Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode. This mode selection affects the accuracy specifications of the ILO oscillator due to supply noise. See Data Sheet for more details.?0: Do not short power domains?1: Short power domains"]
pub struct LFCLK_SHORT_W<'a> {
    w: &'a mut W,
}
impl<'a> LFCLK_SHORT_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
        self.w
    }
}
#[doc = "Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep). Note: this bit is ignored when HIBERNATE_DISABLE=1.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HIBERNATE_A {
    #[doc = "0: No description available"]
    DEEP_SLEEP = 0,
    #[doc = "1: No description available"]
    HIBERNATE = 1,
}
impl From<HIBERNATE_A> for bool {
    #[inline(always)]
    fn from(variant: HIBERNATE_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `HIBERNATE` reader - Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep). Note: this bit is ignored when HIBERNATE_DISABLE=1."]
pub struct HIBERNATE_R(crate::FieldReader<bool, HIBERNATE_A>);
impl HIBERNATE_R {
    pub(crate) fn new(bits: bool) -> Self {
        HIBERNATE_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> HIBERNATE_A {
        match self.bits {
            false => HIBERNATE_A::DEEP_SLEEP,
            true => HIBERNATE_A::HIBERNATE,
        }
    }
    #[doc = "Checks if the value of the field is `DEEP_SLEEP`"]
    #[inline(always)]
    pub fn is_deep_sleep(&self) -> bool {
        **self == HIBERNATE_A::DEEP_SLEEP
    }
    #[doc = "Checks if the value of the field is `HIBERNATE`"]
    #[inline(always)]
    pub fn is_hibernate(&self) -> bool {
        **self == HIBERNATE_A::HIBERNATE
    }
}
impl core::ops::Deref for HIBERNATE_R {
    type Target = crate::FieldReader<bool, HIBERNATE_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `HIBERNATE` writer - Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep). Note: this bit is ignored when HIBERNATE_DISABLE=1."]
pub struct HIBERNATE_W<'a> {
    w: &'a mut W,
}
impl<'a> HIBERNATE_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: HIBERNATE_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn deep_sleep(self) -> &'a mut W {
        self.variant(HIBERNATE_A::DEEP_SLEEP)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn hibernate(self) -> &'a mut W {
        self.variant(HIBERNATE_A::HIBERNATE)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:3 - Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."]
    #[inline(always)]
    pub fn power_mode(&self) -> POWER_MODE_R {
        POWER_MODE_R::new((self.bits & 0x0f) as u8)
    }
    #[doc = "Bit 4 - Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)"]
    #[inline(always)]
    pub fn debug_session(&self) -> DEBUG_SESSION_R {
        DEBUG_SESSION_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 5 - Indicates whether the low power mode regulators are ready to enter DEEPSLEEP or HIBERNATE mode. ?0: If DEEPSLEEP or HIBERNATE mode is requested, device will enter SLEEP mode. When low power regulators are ready, device will automatically enter the originally requested mode.?1: Normal operation. DEEPSLEEP and HIBERNATE work as described."]
    #[inline(always)]
    pub fn lpm_ready(&self) -> LPM_READY_R {
        LPM_READY_R::new(((self.bits >> 5) & 0x01) != 0)
    }
    #[doc = "Bit 23 - Should be set by firmware if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally."]
    #[inline(always)]
    pub fn ext_vccd(&self) -> EXT_VCCD_R {
        EXT_VCCD_R::new(((self.bits >> 23) & 0x01) != 0)
    }
    #[doc = "Bit 24 - 0: HV State Monitoring is disabled?1: HV State Monitoring is automatically enable by sleep controller"]
    #[inline(always)]
    pub fn hvmon_enable(&self) -> HVMON_ENABLE_R {
        HVMON_ENABLE_R::new(((self.bits >> 24) & 0x01) != 0)
    }
    #[doc = "Bit 27 - This bit is asserted during the boot process?0: Forces IMO to operate at 12MHz, ignore its frequency and trim settings and operate independent on its external references.?1: Turns IMO into normal operational mode"]
    #[inline(always)]
    pub fn fimo_disable(&self) -> FIMO_DISABLE_R {
        FIMO_DISABLE_R::new(((self.bits >> 27) & 0x01) != 0)
    }
    #[doc = "Bit 29 - Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode. This mode selection affects the accuracy specifications of the ILO oscillator due to supply noise. See Data Sheet for more details.?0: Do not short power domains?1: Short power domains"]
    #[inline(always)]
    pub fn lfclk_short(&self) -> LFCLK_SHORT_R {
        LFCLK_SHORT_R::new(((self.bits >> 29) & 0x01) != 0)
    }
    #[doc = "Bit 31 - Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep). Note: this bit is ignored when HIBERNATE_DISABLE=1."]
    #[inline(always)]
    pub fn hibernate(&self) -> HIBERNATE_R {
        HIBERNATE_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 23 - Should be set by firmware if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally."]
    #[inline(always)]
    pub fn ext_vccd(&mut self) -> EXT_VCCD_W {
        EXT_VCCD_W { w: self }
    }
    #[doc = "Bit 24 - 0: HV State Monitoring is disabled?1: HV State Monitoring is automatically enable by sleep controller"]
    #[inline(always)]
    pub fn hvmon_enable(&mut self) -> HVMON_ENABLE_W {
        HVMON_ENABLE_W { w: self }
    }
    #[doc = "Bit 25 - Firmware writes 1 to reload HV State in hibernate shadow copy. Hardware clears this bit after reload was successful. Wait at least 9 cycles after writing/recalling NVL before reloading the HVMON."]
    #[inline(always)]
    pub fn hvmon_reload(&mut self) -> HVMON_RELOAD_W {
        HVMON_RELOAD_W { w: self }
    }
    #[doc = "Bit 27 - This bit is asserted during the boot process?0: Forces IMO to operate at 12MHz, ignore its frequency and trim settings and operate independent on its external references.?1: Turns IMO into normal operational mode"]
    #[inline(always)]
    pub fn fimo_disable(&mut self) -> FIMO_DISABLE_W {
        FIMO_DISABLE_W { w: self }
    }
    #[doc = "Bit 28 - 0: Normal operation, HIBERNATE works as described?1: HIBERNATE bit is ignored, Hibernate mode is permanently disabled (part will go to DeepSleep instead.?Note: This bit is a write-once bit until the next reset."]
    #[inline(always)]
    pub fn hibernate_disable(&mut self) -> HIBERNATE_DISABLE_W {
        HIBERNATE_DISABLE_W { w: self }
    }
    #[doc = "Bit 29 - Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode. This mode selection affects the accuracy specifications of the ILO oscillator due to supply noise. See Data Sheet for more details.?0: Do not short power domains?1: Short power domains"]
    #[inline(always)]
    pub fn lfclk_short(&mut self) -> LFCLK_SHORT_W {
        LFCLK_SHORT_W { w: self }
    }
    #[doc = "Bit 31 - Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep). Note: this bit is ignored when HIBERNATE_DISABLE=1."]
    #[inline(always)]
    pub fn hibernate(&mut self) -> HIBERNATE_W {
        HIBERNATE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Power Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwr_control](index.html) module"]
pub struct PWR_CONTROL_SPEC;
impl crate::RegisterSpec for PWR_CONTROL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pwr_control::R](R) reader structure"]
impl crate::Readable for PWR_CONTROL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pwr_control::W](W) writer structure"]
impl crate::Writable for PWR_CONTROL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets PWR_CONTROL to value 0"]
impl crate::Resettable for PWR_CONTROL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
