#[doc = "Register `CLK_IMO_CONFIG` reader"]
pub struct R(crate::R<CLK_IMO_CONFIG_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CLK_IMO_CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CLK_IMO_CONFIG_SPEC>> for R {
    fn from(reader: crate::R<CLK_IMO_CONFIG_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CLK_IMO_CONFIG` writer"]
pub struct W(crate::W<CLK_IMO_CONFIG_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CLK_IMO_CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CLK_IMO_CONFIG_SPEC>> for W {
    fn from(writer: crate::W<CLK_IMO_CONFIG_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Selects operating source for SPCIF Timer/Flash Pump clock.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLASHPUMP_SEL_A {
    #[doc = "0: No description available"]
    GND = 0,
    #[doc = "1: No description available"]
    CLK36 = 1,
}
impl From<FLASHPUMP_SEL_A> for bool {
    #[inline(always)]
    fn from(variant: FLASHPUMP_SEL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `FLASHPUMP_SEL` reader - Selects operating source for SPCIF Timer/Flash Pump clock."]
pub struct FLASHPUMP_SEL_R(crate::FieldReader<bool, FLASHPUMP_SEL_A>);
impl FLASHPUMP_SEL_R {
    pub(crate) fn new(bits: bool) -> Self {
        FLASHPUMP_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> FLASHPUMP_SEL_A {
        match self.bits {
            false => FLASHPUMP_SEL_A::GND,
            true => FLASHPUMP_SEL_A::CLK36,
        }
    }
    #[doc = "Checks if the value of the field is `GND`"]
    #[inline(always)]
    pub fn is_gnd(&self) -> bool {
        **self == FLASHPUMP_SEL_A::GND
    }
    #[doc = "Checks if the value of the field is `CLK36`"]
    #[inline(always)]
    pub fn is_clk36(&self) -> bool {
        **self == FLASHPUMP_SEL_A::CLK36
    }
}
impl core::ops::Deref for FLASHPUMP_SEL_R {
    type Target = crate::FieldReader<bool, FLASHPUMP_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `FLASHPUMP_SEL` writer - Selects operating source for SPCIF Timer/Flash Pump clock."]
pub struct FLASHPUMP_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> FLASHPUMP_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: FLASHPUMP_SEL_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gnd(self) -> &'a mut W {
        self.variant(FLASHPUMP_SEL_A::GND)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn clk36(self) -> &'a mut W {
        self.variant(FLASHPUMP_SEL_A::CLK36)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
        self.w
    }
}
#[doc = "Field `EN_FASTBIAS` reader - Forces the FIMO's fast bias circuits to remain powered (engineering only). This bit must be cleared by BootROM after FIMO is no longer required."]
pub struct EN_FASTBIAS_R(crate::FieldReader<bool, bool>);
impl EN_FASTBIAS_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_FASTBIAS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EN_FASTBIAS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_FASTBIAS` writer - Forces the FIMO's fast bias circuits to remain powered (engineering only). This bit must be cleared by BootROM after FIMO is no longer required."]
pub struct EN_FASTBIAS_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_FASTBIAS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
        self.w
    }
}
#[doc = "Field `TEST_FASTBIAS` reader - Forces the IMO into FIMO mode (engineering only). Only works when EN_FASTBIAS=1."]
pub struct TEST_FASTBIAS_R(crate::FieldReader<bool, bool>);
impl TEST_FASTBIAS_R {
    pub(crate) fn new(bits: bool) -> Self {
        TEST_FASTBIAS_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for TEST_FASTBIAS_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `TEST_FASTBIAS` writer - Forces the IMO into FIMO mode (engineering only). Only works when EN_FASTBIAS=1."]
pub struct TEST_FASTBIAS_W<'a> {
    w: &'a mut W,
}
impl<'a> TEST_FASTBIAS_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
        self.w
    }
}
#[doc = "Selects operating source for Pump clock. This clock is not guaranteed to be glitch free when changing IMO parameters or clock divider settings.?5-7: reserved, do not use\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum PUMP_SEL_A {
    #[doc = "0: No description available"]
    GND = 0,
    #[doc = "1: No description available"]
    IMO = 1,
    #[doc = "2: No description available"]
    DBL = 2,
    #[doc = "3: No description available"]
    CLK36 = 3,
    #[doc = "4: No description available"]
    FF1 = 4,
}
impl From<PUMP_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: PUMP_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `PUMP_SEL` reader - Selects operating source for Pump clock. This clock is not guaranteed to be glitch free when changing IMO parameters or clock divider settings.?5-7: reserved, do not use"]
pub struct PUMP_SEL_R(crate::FieldReader<u8, PUMP_SEL_A>);
impl PUMP_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        PUMP_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<PUMP_SEL_A> {
        match self.bits {
            0 => Some(PUMP_SEL_A::GND),
            1 => Some(PUMP_SEL_A::IMO),
            2 => Some(PUMP_SEL_A::DBL),
            3 => Some(PUMP_SEL_A::CLK36),
            4 => Some(PUMP_SEL_A::FF1),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `GND`"]
    #[inline(always)]
    pub fn is_gnd(&self) -> bool {
        **self == PUMP_SEL_A::GND
    }
    #[doc = "Checks if the value of the field is `IMO`"]
    #[inline(always)]
    pub fn is_imo(&self) -> bool {
        **self == PUMP_SEL_A::IMO
    }
    #[doc = "Checks if the value of the field is `DBL`"]
    #[inline(always)]
    pub fn is_dbl(&self) -> bool {
        **self == PUMP_SEL_A::DBL
    }
    #[doc = "Checks if the value of the field is `CLK36`"]
    #[inline(always)]
    pub fn is_clk36(&self) -> bool {
        **self == PUMP_SEL_A::CLK36
    }
    #[doc = "Checks if the value of the field is `FF1`"]
    #[inline(always)]
    pub fn is_ff1(&self) -> bool {
        **self == PUMP_SEL_A::FF1
    }
}
impl core::ops::Deref for PUMP_SEL_R {
    type Target = crate::FieldReader<u8, PUMP_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `PUMP_SEL` writer - Selects operating source for Pump clock. This clock is not guaranteed to be glitch free when changing IMO parameters or clock divider settings.?5-7: reserved, do not use"]
pub struct PUMP_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> PUMP_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PUMP_SEL_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn gnd(self) -> &'a mut W {
        self.variant(PUMP_SEL_A::GND)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn imo(self) -> &'a mut W {
        self.variant(PUMP_SEL_A::IMO)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn dbl(self) -> &'a mut W {
        self.variant(PUMP_SEL_A::DBL)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn clk36(self) -> &'a mut W {
        self.variant(PUMP_SEL_A::CLK36)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn ff1(self) -> &'a mut W {
        self.variant(PUMP_SEL_A::FF1)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 25)) | ((value as u32 & 0x07) << 25);
        self.w
    }
}
#[doc = "Field `TEST_USB_MODE` reader - Forces IMO into locking mode. Engineering only.?1: Software can write FSOFFSET, OFFSET, and GAIN settings for characterization. Hardware updates to these registers are not blocked, so disable peripheral updates if they are not desired.?0: Normal operation. IMO operates in either normal or locking mode, depending on settings for the selected external locking peripheral."]
pub struct TEST_USB_MODE_R(crate::FieldReader<bool, bool>);
impl TEST_USB_MODE_R {
    pub(crate) fn new(bits: bool) -> Self {
        TEST_USB_MODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for TEST_USB_MODE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `TEST_USB_MODE` writer - Forces IMO into locking mode. Engineering only.?1: Software can write FSOFFSET, OFFSET, and GAIN settings for characterization. Hardware updates to these registers are not blocked, so disable peripheral updates if they are not desired.?0: Normal operation. IMO operates in either normal or locking mode, depending on settings for the selected external locking peripheral."]
pub struct TEST_USB_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> TEST_USB_MODE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
        self.w
    }
}
#[doc = "Field `EN_CLK36` reader - Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump. Note: Since there are two consumers of the 36MHz clock, care should be taken when clearing this bit. The correct procedure for clearing this bit is:?1. Disable interrupts?2. Check if both FLASHPUMP_SEL<>1 and PUMP_SEL<>3?3. If so, set EN_CLK36=0?4. Enable interrupts"]
pub struct EN_CLK36_R(crate::FieldReader<bool, bool>);
impl EN_CLK36_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_CLK36_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EN_CLK36_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_CLK36` writer - Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump. Note: Since there are two consumers of the 36MHz clock, care should be taken when clearing this bit. The correct procedure for clearing this bit is:?1. Disable interrupts?2. Check if both FLASHPUMP_SEL<>1 and PUMP_SEL<>3?3. If so, set EN_CLK36=0?4. Enable interrupts"]
pub struct EN_CLK36_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_CLK36_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
        self.w
    }
}
#[doc = "Field `EN_CLK2X` reader - Enables main oscillator doubler circuit that can be used for TSS Charge Pumps. This circuit is not available to generate any digital clocks."]
pub struct EN_CLK2X_R(crate::FieldReader<bool, bool>);
impl EN_CLK2X_R {
    pub(crate) fn new(bits: bool) -> Self {
        EN_CLK2X_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EN_CLK2X_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EN_CLK2X` writer - Enables main oscillator doubler circuit that can be used for TSS Charge Pumps. This circuit is not available to generate any digital clocks."]
pub struct EN_CLK2X_W<'a> {
    w: &'a mut W,
}
impl<'a> EN_CLK2X_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
        self.w
    }
}
#[doc = "Field `ENABLE` reader - Master enable for IMO oscillator. Clearing this bit will disable the IMO but not disconnect it from the power rail. This bit can also be used during IDDQ testing."]
pub struct ENABLE_R(crate::FieldReader<bool, bool>);
impl ENABLE_R {
    pub(crate) fn new(bits: bool) -> Self {
        ENABLE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ENABLE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ENABLE` writer - Master enable for IMO oscillator. Clearing this bit will disable the IMO but not disconnect it from the power rail. This bit can also be used during IDDQ testing."]
pub struct ENABLE_W<'a> {
    w: &'a mut W,
}
impl<'a> ENABLE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
        self.w
    }
}
impl R {
    #[doc = "Bit 22 - Selects operating source for SPCIF Timer/Flash Pump clock."]
    #[inline(always)]
    pub fn flashpump_sel(&self) -> FLASHPUMP_SEL_R {
        FLASHPUMP_SEL_R::new(((self.bits >> 22) & 0x01) != 0)
    }
    #[doc = "Bit 23 - Forces the FIMO's fast bias circuits to remain powered (engineering only). This bit must be cleared by BootROM after FIMO is no longer required."]
    #[inline(always)]
    pub fn en_fastbias(&self) -> EN_FASTBIAS_R {
        EN_FASTBIAS_R::new(((self.bits >> 23) & 0x01) != 0)
    }
    #[doc = "Bit 24 - Forces the IMO into FIMO mode (engineering only). Only works when EN_FASTBIAS=1."]
    #[inline(always)]
    pub fn test_fastbias(&self) -> TEST_FASTBIAS_R {
        TEST_FASTBIAS_R::new(((self.bits >> 24) & 0x01) != 0)
    }
    #[doc = "Bits 25:27 - Selects operating source for Pump clock. This clock is not guaranteed to be glitch free when changing IMO parameters or clock divider settings.?5-7: reserved, do not use"]
    #[inline(always)]
    pub fn pump_sel(&self) -> PUMP_SEL_R {
        PUMP_SEL_R::new(((self.bits >> 25) & 0x07) as u8)
    }
    #[doc = "Bit 28 - Forces IMO into locking mode. Engineering only.?1: Software can write FSOFFSET, OFFSET, and GAIN settings for characterization. Hardware updates to these registers are not blocked, so disable peripheral updates if they are not desired.?0: Normal operation. IMO operates in either normal or locking mode, depending on settings for the selected external locking peripheral."]
    #[inline(always)]
    pub fn test_usb_mode(&self) -> TEST_USB_MODE_R {
        TEST_USB_MODE_R::new(((self.bits >> 28) & 0x01) != 0)
    }
    #[doc = "Bit 29 - Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump. Note: Since there are two consumers of the 36MHz clock, care should be taken when clearing this bit. The correct procedure for clearing this bit is:?1. Disable interrupts?2. Check if both FLASHPUMP_SEL<>1 and PUMP_SEL<>3?3. If so, set EN_CLK36=0?4. Enable interrupts"]
    #[inline(always)]
    pub fn en_clk36(&self) -> EN_CLK36_R {
        EN_CLK36_R::new(((self.bits >> 29) & 0x01) != 0)
    }
    #[doc = "Bit 30 - Enables main oscillator doubler circuit that can be used for TSS Charge Pumps. This circuit is not available to generate any digital clocks."]
    #[inline(always)]
    pub fn en_clk2x(&self) -> EN_CLK2X_R {
        EN_CLK2X_R::new(((self.bits >> 30) & 0x01) != 0)
    }
    #[doc = "Bit 31 - Master enable for IMO oscillator. Clearing this bit will disable the IMO but not disconnect it from the power rail. This bit can also be used during IDDQ testing."]
    #[inline(always)]
    pub fn enable(&self) -> ENABLE_R {
        ENABLE_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 22 - Selects operating source for SPCIF Timer/Flash Pump clock."]
    #[inline(always)]
    pub fn flashpump_sel(&mut self) -> FLASHPUMP_SEL_W {
        FLASHPUMP_SEL_W { w: self }
    }
    #[doc = "Bit 23 - Forces the FIMO's fast bias circuits to remain powered (engineering only). This bit must be cleared by BootROM after FIMO is no longer required."]
    #[inline(always)]
    pub fn en_fastbias(&mut self) -> EN_FASTBIAS_W {
        EN_FASTBIAS_W { w: self }
    }
    #[doc = "Bit 24 - Forces the IMO into FIMO mode (engineering only). Only works when EN_FASTBIAS=1."]
    #[inline(always)]
    pub fn test_fastbias(&mut self) -> TEST_FASTBIAS_W {
        TEST_FASTBIAS_W { w: self }
    }
    #[doc = "Bits 25:27 - Selects operating source for Pump clock. This clock is not guaranteed to be glitch free when changing IMO parameters or clock divider settings.?5-7: reserved, do not use"]
    #[inline(always)]
    pub fn pump_sel(&mut self) -> PUMP_SEL_W {
        PUMP_SEL_W { w: self }
    }
    #[doc = "Bit 28 - Forces IMO into locking mode. Engineering only.?1: Software can write FSOFFSET, OFFSET, and GAIN settings for characterization. Hardware updates to these registers are not blocked, so disable peripheral updates if they are not desired.?0: Normal operation. IMO operates in either normal or locking mode, depending on settings for the selected external locking peripheral."]
    #[inline(always)]
    pub fn test_usb_mode(&mut self) -> TEST_USB_MODE_W {
        TEST_USB_MODE_W { w: self }
    }
    #[doc = "Bit 29 - Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump. Note: Since there are two consumers of the 36MHz clock, care should be taken when clearing this bit. The correct procedure for clearing this bit is:?1. Disable interrupts?2. Check if both FLASHPUMP_SEL<>1 and PUMP_SEL<>3?3. If so, set EN_CLK36=0?4. Enable interrupts"]
    #[inline(always)]
    pub fn en_clk36(&mut self) -> EN_CLK36_W {
        EN_CLK36_W { w: self }
    }
    #[doc = "Bit 30 - Enables main oscillator doubler circuit that can be used for TSS Charge Pumps. This circuit is not available to generate any digital clocks."]
    #[inline(always)]
    pub fn en_clk2x(&mut self) -> EN_CLK2X_W {
        EN_CLK2X_W { w: self }
    }
    #[doc = "Bit 31 - Master enable for IMO oscillator. Clearing this bit will disable the IMO but not disconnect it from the power rail. This bit can also be used during IDDQ testing."]
    #[inline(always)]
    pub fn enable(&mut self) -> ENABLE_W {
        ENABLE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "IMO Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_imo_config](index.html) module"]
pub struct CLK_IMO_CONFIG_SPEC;
impl crate::RegisterSpec for CLK_IMO_CONFIG_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [clk_imo_config::R](R) reader structure"]
impl crate::Readable for CLK_IMO_CONFIG_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [clk_imo_config::W](W) writer structure"]
impl crate::Writable for CLK_IMO_CONFIG_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CLK_IMO_CONFIG to value 0"]
impl crate::Resettable for CLK_IMO_CONFIG_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
