#[doc = "Register `CONFIG` reader"]
pub struct R(crate::R<CONFIG_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CONFIG_SPEC>> for R {
    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CONFIG` writer"]
pub struct W(crate::W<CONFIG_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CONFIG_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CONFIG_SPEC>> for W {
    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `EDGE_MODE` reader - CAN bus synchronization logic??0?: Edge from ?R? to ?D? is used for synchronization??1?: Both edges are used?Note, only ?R? to ?D? edge shall be used for synchronization per ISO-11898-1 spec, so this bit should always be set 0 (by default)"]
pub struct EDGE_MODE_R(crate::FieldReader<bool, bool>);
impl EDGE_MODE_R {
    pub(crate) fn new(bits: bool) -> Self {
        EDGE_MODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for EDGE_MODE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `EDGE_MODE` writer - CAN bus synchronization logic??0?: Edge from ?R? to ?D? is used for synchronization??1?: Both edges are used?Note, only ?R? to ?D? edge shall be used for synchronization per ISO-11898-1 spec, so this bit should always be set 0 (by default)"]
pub struct EDGE_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> EDGE_MODE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
}
#[doc = "Field `SAMPLING_MODE` reader - CAN bus bit sampling??0?: One sampling point is used in the receiver?path??1?: 3 sampling points with majority decision are?used"]
pub struct SAMPLING_MODE_R(crate::FieldReader<bool, bool>);
impl SAMPLING_MODE_R {
    pub(crate) fn new(bits: bool) -> Self {
        SAMPLING_MODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for SAMPLING_MODE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SAMPLING_MODE` writer - CAN bus bit sampling??0?: One sampling point is used in the receiver?path??1?: 3 sampling points with majority decision are?used"]
pub struct SAMPLING_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> SAMPLING_MODE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
        self.w
    }
}
#[doc = "Field `CFG_SJW` reader - Synchronization jump width - 1?sjw = tseg1 and sjw = tseg2"]
pub struct CFG_SJW_R(crate::FieldReader<u8, u8>);
impl CFG_SJW_R {
    pub(crate) fn new(bits: u8) -> Self {
        CFG_SJW_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CFG_SJW_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CFG_SJW` writer - Synchronization jump width - 1?sjw = tseg1 and sjw = tseg2"]
pub struct CFG_SJW_W<'a> {
    w: &'a mut W,
}
impl<'a> CFG_SJW_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
        self.w
    }
}
#[doc = "Field `AUTO_RESTART` reader - ?0?: After bus-off, the CAN core must be restarted by setting ? COMMAND.RUN register. This is the recommended setting.??1?: After bus-off, the CAN core is restarting automatically ? after 128 groups of 11 recessive bits"]
pub struct AUTO_RESTART_R(crate::FieldReader<bool, bool>);
impl AUTO_RESTART_R {
    pub(crate) fn new(bits: bool) -> Self {
        AUTO_RESTART_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for AUTO_RESTART_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `AUTO_RESTART` writer - ?0?: After bus-off, the CAN core must be restarted by setting ? COMMAND.RUN register. This is the recommended setting.??1?: After bus-off, the CAN core is restarting automatically ? after 128 groups of 11 recessive bits"]
pub struct AUTO_RESTART_W<'a> {
    w: &'a mut W,
}
impl<'a> AUTO_RESTART_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
        self.w
    }
}
#[doc = "Field `CFG_TSEG2` reader - Time segment 2?Length of the second time segment:?tseg2 = cfg_tseg2 + 1?cfg_tseg2=0 is not allowed; cfg_tseg2=1 is only?allowed in direct sampling mode."]
pub struct CFG_TSEG2_R(crate::FieldReader<u8, u8>);
impl CFG_TSEG2_R {
    pub(crate) fn new(bits: u8) -> Self {
        CFG_TSEG2_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CFG_TSEG2_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CFG_TSEG2` writer - Time segment 2?Length of the second time segment:?tseg2 = cfg_tseg2 + 1?cfg_tseg2=0 is not allowed; cfg_tseg2=1 is only?allowed in direct sampling mode."]
pub struct CFG_TSEG2_W<'a> {
    w: &'a mut W,
}
impl<'a> CFG_TSEG2_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5);
        self.w
    }
}
#[doc = "Field `CFG_TSEG1` reader - Time segment 1?Length of the first time segment:?tseg1 = cfg_tseg1 + 1?Time segment 1 includes the propagation time.?cfg_tseg1=0 and cfg_tseg1=1 are not allowed."]
pub struct CFG_TSEG1_R(crate::FieldReader<u8, u8>);
impl CFG_TSEG1_R {
    pub(crate) fn new(bits: u8) -> Self {
        CFG_TSEG1_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CFG_TSEG1_R {
    type Target = crate::FieldReader<u8, u8>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CFG_TSEG1` writer - Time segment 1?Length of the first time segment:?tseg1 = cfg_tseg1 + 1?Time segment 1 includes the propagation time.?cfg_tseg1=0 and cfg_tseg1=1 are not allowed."]
pub struct CFG_TSEG1_W<'a> {
    w: &'a mut W,
}
impl<'a> CFG_TSEG1_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
        self.w
    }
}
#[doc = "Field `CFG_ARBITER` reader - Transmit buffer arbiter??0?: Round robin arbitration??1?: Fixed priority arbitration"]
pub struct CFG_ARBITER_R(crate::FieldReader<bool, bool>);
impl CFG_ARBITER_R {
    pub(crate) fn new(bits: bool) -> Self {
        CFG_ARBITER_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CFG_ARBITER_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CFG_ARBITER` writer - Transmit buffer arbiter??0?: Round robin arbitration??1?: Fixed priority arbitration"]
pub struct CFG_ARBITER_W<'a> {
    w: &'a mut W,
}
impl<'a> CFG_ARBITER_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
        self.w
    }
}
#[doc = "Field `SWAP_ENDIAN` reader - Swap Endian - the byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol?0: CAN data byte position is not swapped (big endian)?1: CAN data byte position is swapped (little endian)"]
pub struct SWAP_ENDIAN_R(crate::FieldReader<bool, bool>);
impl SWAP_ENDIAN_R {
    pub(crate) fn new(bits: bool) -> Self {
        SWAP_ENDIAN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for SWAP_ENDIAN_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `SWAP_ENDIAN` writer - Swap Endian - the byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol?0: CAN data byte position is not swapped (big endian)?1: CAN data byte position is swapped (little endian)"]
pub struct SWAP_ENDIAN_W<'a> {
    w: &'a mut W,
}
impl<'a> SWAP_ENDIAN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
        self.w
    }
}
#[doc = "Field `ECR_MODE` reader - Error Capture mode?0: Free running: The ECR register shows the current bit position within the CAN frame?1: Capture mode: The ecr register shows the bit position and type of the last captured CAN error."]
pub struct ECR_MODE_R(crate::FieldReader<bool, bool>);
impl ECR_MODE_R {
    pub(crate) fn new(bits: bool) -> Self {
        ECR_MODE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for ECR_MODE_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `ECR_MODE` writer - Error Capture mode?0: Free running: The ECR register shows the current bit position within the CAN frame?1: Capture mode: The ecr register shows the bit position and type of the last captured CAN error."]
pub struct ECR_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> ECR_MODE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
        self.w
    }
}
#[doc = "Field `CFG_BITRATE` reader - Prescaler for generating the time quantum?which defines the TQ:?0: One time quantum equals 1 clock cycle?1: One time quantum equals 2 clock cycles?...?32767: One time quantum equals 32768 clock?cycles"]
pub struct CFG_BITRATE_R(crate::FieldReader<u16, u16>);
impl CFG_BITRATE_R {
    pub(crate) fn new(bits: u16) -> Self {
        CFG_BITRATE_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CFG_BITRATE_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CFG_BITRATE` writer - Prescaler for generating the time quantum?which defines the TQ:?0: One time quantum equals 1 clock cycle?1: One time quantum equals 2 clock cycles?...?32767: One time quantum equals 32768 clock?cycles"]
pub struct CFG_BITRATE_W<'a> {
    w: &'a mut W,
}
impl<'a> CFG_BITRATE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x7fff << 16)) | ((value as u32 & 0x7fff) << 16);
        self.w
    }
}
impl R {
    #[doc = "Bit 0 - CAN bus synchronization logic??0?: Edge from ?R? to ?D? is used for synchronization??1?: Both edges are used?Note, only ?R? to ?D? edge shall be used for synchronization per ISO-11898-1 spec, so this bit should always be set 0 (by default)"]
    #[inline(always)]
    pub fn edge_mode(&self) -> EDGE_MODE_R {
        EDGE_MODE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - CAN bus bit sampling??0?: One sampling point is used in the receiver?path??1?: 3 sampling points with majority decision are?used"]
    #[inline(always)]
    pub fn sampling_mode(&self) -> SAMPLING_MODE_R {
        SAMPLING_MODE_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bits 2:3 - Synchronization jump width - 1?sjw = tseg1 and sjw = tseg2"]
    #[inline(always)]
    pub fn cfg_sjw(&self) -> CFG_SJW_R {
        CFG_SJW_R::new(((self.bits >> 2) & 0x03) as u8)
    }
    #[doc = "Bit 4 - ?0?: After bus-off, the CAN core must be restarted by setting ? COMMAND.RUN register. This is the recommended setting.??1?: After bus-off, the CAN core is restarting automatically ? after 128 groups of 11 recessive bits"]
    #[inline(always)]
    pub fn auto_restart(&self) -> AUTO_RESTART_R {
        AUTO_RESTART_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bits 5:7 - Time segment 2?Length of the second time segment:?tseg2 = cfg_tseg2 + 1?cfg_tseg2=0 is not allowed; cfg_tseg2=1 is only?allowed in direct sampling mode."]
    #[inline(always)]
    pub fn cfg_tseg2(&self) -> CFG_TSEG2_R {
        CFG_TSEG2_R::new(((self.bits >> 5) & 0x07) as u8)
    }
    #[doc = "Bits 8:11 - Time segment 1?Length of the first time segment:?tseg1 = cfg_tseg1 + 1?Time segment 1 includes the propagation time.?cfg_tseg1=0 and cfg_tseg1=1 are not allowed."]
    #[inline(always)]
    pub fn cfg_tseg1(&self) -> CFG_TSEG1_R {
        CFG_TSEG1_R::new(((self.bits >> 8) & 0x0f) as u8)
    }
    #[doc = "Bit 12 - Transmit buffer arbiter??0?: Round robin arbitration??1?: Fixed priority arbitration"]
    #[inline(always)]
    pub fn cfg_arbiter(&self) -> CFG_ARBITER_R {
        CFG_ARBITER_R::new(((self.bits >> 12) & 0x01) != 0)
    }
    #[doc = "Bit 13 - Swap Endian - the byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol?0: CAN data byte position is not swapped (big endian)?1: CAN data byte position is swapped (little endian)"]
    #[inline(always)]
    pub fn swap_endian(&self) -> SWAP_ENDIAN_R {
        SWAP_ENDIAN_R::new(((self.bits >> 13) & 0x01) != 0)
    }
    #[doc = "Bit 14 - Error Capture mode?0: Free running: The ECR register shows the current bit position within the CAN frame?1: Capture mode: The ecr register shows the bit position and type of the last captured CAN error."]
    #[inline(always)]
    pub fn ecr_mode(&self) -> ECR_MODE_R {
        ECR_MODE_R::new(((self.bits >> 14) & 0x01) != 0)
    }
    #[doc = "Bits 16:30 - Prescaler for generating the time quantum?which defines the TQ:?0: One time quantum equals 1 clock cycle?1: One time quantum equals 2 clock cycles?...?32767: One time quantum equals 32768 clock?cycles"]
    #[inline(always)]
    pub fn cfg_bitrate(&self) -> CFG_BITRATE_R {
        CFG_BITRATE_R::new(((self.bits >> 16) & 0x7fff) as u16)
    }
}
impl W {
    #[doc = "Bit 0 - CAN bus synchronization logic??0?: Edge from ?R? to ?D? is used for synchronization??1?: Both edges are used?Note, only ?R? to ?D? edge shall be used for synchronization per ISO-11898-1 spec, so this bit should always be set 0 (by default)"]
    #[inline(always)]
    pub fn edge_mode(&mut self) -> EDGE_MODE_W {
        EDGE_MODE_W { w: self }
    }
    #[doc = "Bit 1 - CAN bus bit sampling??0?: One sampling point is used in the receiver?path??1?: 3 sampling points with majority decision are?used"]
    #[inline(always)]
    pub fn sampling_mode(&mut self) -> SAMPLING_MODE_W {
        SAMPLING_MODE_W { w: self }
    }
    #[doc = "Bits 2:3 - Synchronization jump width - 1?sjw = tseg1 and sjw = tseg2"]
    #[inline(always)]
    pub fn cfg_sjw(&mut self) -> CFG_SJW_W {
        CFG_SJW_W { w: self }
    }
    #[doc = "Bit 4 - ?0?: After bus-off, the CAN core must be restarted by setting ? COMMAND.RUN register. This is the recommended setting.??1?: After bus-off, the CAN core is restarting automatically ? after 128 groups of 11 recessive bits"]
    #[inline(always)]
    pub fn auto_restart(&mut self) -> AUTO_RESTART_W {
        AUTO_RESTART_W { w: self }
    }
    #[doc = "Bits 5:7 - Time segment 2?Length of the second time segment:?tseg2 = cfg_tseg2 + 1?cfg_tseg2=0 is not allowed; cfg_tseg2=1 is only?allowed in direct sampling mode."]
    #[inline(always)]
    pub fn cfg_tseg2(&mut self) -> CFG_TSEG2_W {
        CFG_TSEG2_W { w: self }
    }
    #[doc = "Bits 8:11 - Time segment 1?Length of the first time segment:?tseg1 = cfg_tseg1 + 1?Time segment 1 includes the propagation time.?cfg_tseg1=0 and cfg_tseg1=1 are not allowed."]
    #[inline(always)]
    pub fn cfg_tseg1(&mut self) -> CFG_TSEG1_W {
        CFG_TSEG1_W { w: self }
    }
    #[doc = "Bit 12 - Transmit buffer arbiter??0?: Round robin arbitration??1?: Fixed priority arbitration"]
    #[inline(always)]
    pub fn cfg_arbiter(&mut self) -> CFG_ARBITER_W {
        CFG_ARBITER_W { w: self }
    }
    #[doc = "Bit 13 - Swap Endian - the byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol?0: CAN data byte position is not swapped (big endian)?1: CAN data byte position is swapped (little endian)"]
    #[inline(always)]
    pub fn swap_endian(&mut self) -> SWAP_ENDIAN_W {
        SWAP_ENDIAN_W { w: self }
    }
    #[doc = "Bit 14 - Error Capture mode?0: Free running: The ECR register shows the current bit position within the CAN frame?1: Capture mode: The ecr register shows the bit position and type of the last captured CAN error."]
    #[inline(always)]
    pub fn ecr_mode(&mut self) -> ECR_MODE_W {
        ECR_MODE_W { w: self }
    }
    #[doc = "Bits 16:30 - Prescaler for generating the time quantum?which defines the TQ:?0: One time quantum equals 1 clock cycle?1: One time quantum equals 2 clock cycles?...?32767: One time quantum equals 32768 clock?cycles"]
    #[inline(always)]
    pub fn cfg_bitrate(&mut self) -> CFG_BITRATE_W {
        CFG_BITRATE_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "CAN Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
pub struct CONFIG_SPEC;
impl crate::RegisterSpec for CONFIG_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [config::R](R) reader structure"]
impl crate::Readable for CONFIG_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
impl crate::Writable for CONFIG_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CONFIG to value 0"]
impl crate::Resettable for CONFIG_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
