#[doc = "Register `CFG18` reader"]
pub struct R(crate::R<CFG18_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG18_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG18_SPEC>> for R {
    fn from(reader: crate::R<CFG18_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG18` writer"]
pub struct W(crate::W<CFG18_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG18_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG18_SPEC>> for W {
    fn from(writer: crate::W<CFG18_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CTL_MD0_A {
    #[doc = "0: No description available"]
    DIRECT = 0,
    #[doc = "1: No description available"]
    SYNC = 1,
    #[doc = "2: No description available"]
    DOUBLE_SYNC = 2,
    #[doc = "3: No description available"]
    PULSE = 3,
}
impl From<CTL_MD0_A> for u8 {
    #[inline(always)]
    fn from(variant: CTL_MD0_A) -> Self {
        variant as _
    }
}
#[doc = "Field `CTL_MD0` reader - CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register."]
pub struct CTL_MD0_R(crate::FieldReader<u8, CTL_MD0_A>);
impl CTL_MD0_R {
    pub(crate) fn new(bits: u8) -> Self {
        CTL_MD0_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> Option<CTL_MD0_A> {
        match self.bits {
            0 => Some(CTL_MD0_A::DIRECT),
            1 => Some(CTL_MD0_A::SYNC),
            2 => Some(CTL_MD0_A::DOUBLE_SYNC),
            3 => Some(CTL_MD0_A::PULSE),
            _ => None,
        }
    }
    #[doc = "Checks if the value of the field is `DIRECT`"]
    #[inline(always)]
    pub fn is_direct(&self) -> bool {
        **self == CTL_MD0_A::DIRECT
    }
    #[doc = "Checks if the value of the field is `SYNC`"]
    #[inline(always)]
    pub fn is_sync(&self) -> bool {
        **self == CTL_MD0_A::SYNC
    }
    #[doc = "Checks if the value of the field is `DOUBLE_SYNC`"]
    #[inline(always)]
    pub fn is_double_sync(&self) -> bool {
        **self == CTL_MD0_A::DOUBLE_SYNC
    }
    #[doc = "Checks if the value of the field is `PULSE`"]
    #[inline(always)]
    pub fn is_pulse(&self) -> bool {
        **self == CTL_MD0_A::PULSE
    }
}
impl core::ops::Deref for CTL_MD0_R {
    type Target = crate::FieldReader<u8, CTL_MD0_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `CTL_MD0` writer - CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register."]
pub struct CTL_MD0_W<'a> {
    w: &'a mut W,
}
impl<'a> CTL_MD0_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CTL_MD0_A) -> &'a mut W {
        unsafe { self.bits(variant.into()) }
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn direct(self) -> &'a mut W {
        self.variant(CTL_MD0_A::DIRECT)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn sync(self) -> &'a mut W {
        self.variant(CTL_MD0_A::SYNC)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn double_sync(self) -> &'a mut W {
        self.variant(CTL_MD0_A::DOUBLE_SYNC)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn pulse(self) -> &'a mut W {
        self.variant(CTL_MD0_A::PULSE)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | (value as u8 & 0xff);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:7 - CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register."]
    #[inline(always)]
    pub fn ctl_md0(&self) -> CTL_MD0_R {
        CTL_MD0_R::new((self.bits & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bits 0:7 - CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register."]
    #[inline(always)]
    pub fn ctl_md0(&mut self) -> CTL_MD0_W {
        CTL_MD0_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Control Register Mode 0 (used in conjunction with Control Register Mode 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg18](index.html) module"]
pub struct CFG18_SPEC;
impl crate::RegisterSpec for CFG18_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg18::R](R) reader structure"]
impl crate::Readable for CFG18_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg18::W](W) writer structure"]
impl crate::Writable for CFG18_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG18 to value 0"]
impl crate::Resettable for CFG18_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
