#[doc = "Register `CFG26` reader"]
pub struct R(crate::R<CFG26_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<CFG26_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<CFG26_SPEC>> for R {
    fn from(reader: crate::R<CFG26_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `CFG26` writer"]
pub struct W(crate::W<CFG26_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<CFG26_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<CFG26_SPEC>> for W {
    fn from(writer: crate::W<CFG26_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Selects channel route for enable control to the associated UDB component block\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum RC_EN_SEL_A {
    #[doc = "0: No description available"]
    RC_IN0 = 0,
    #[doc = "1: No description available"]
    RC_IN1 = 1,
    #[doc = "2: No description available"]
    RC_IN2 = 2,
    #[doc = "3: No description available"]
    RC_IN3 = 3,
}
impl From<RC_EN_SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: RC_EN_SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Field `RC_EN_SEL` reader - Selects channel route for enable control to the associated UDB component block"]
pub struct RC_EN_SEL_R(crate::FieldReader<u8, RC_EN_SEL_A>);
impl RC_EN_SEL_R {
    pub(crate) fn new(bits: u8) -> Self {
        RC_EN_SEL_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RC_EN_SEL_A {
        match self.bits {
            0 => RC_EN_SEL_A::RC_IN0,
            1 => RC_EN_SEL_A::RC_IN1,
            2 => RC_EN_SEL_A::RC_IN2,
            3 => RC_EN_SEL_A::RC_IN3,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `RC_IN0`"]
    #[inline(always)]
    pub fn is_rc_in0(&self) -> bool {
        **self == RC_EN_SEL_A::RC_IN0
    }
    #[doc = "Checks if the value of the field is `RC_IN1`"]
    #[inline(always)]
    pub fn is_rc_in1(&self) -> bool {
        **self == RC_EN_SEL_A::RC_IN1
    }
    #[doc = "Checks if the value of the field is `RC_IN2`"]
    #[inline(always)]
    pub fn is_rc_in2(&self) -> bool {
        **self == RC_EN_SEL_A::RC_IN2
    }
    #[doc = "Checks if the value of the field is `RC_IN3`"]
    #[inline(always)]
    pub fn is_rc_in3(&self) -> bool {
        **self == RC_EN_SEL_A::RC_IN3
    }
}
impl core::ops::Deref for RC_EN_SEL_R {
    type Target = crate::FieldReader<u8, RC_EN_SEL_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_EN_SEL` writer - Selects channel route for enable control to the associated UDB component block"]
pub struct RC_EN_SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_EN_SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RC_EN_SEL_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in0(self) -> &'a mut W {
        self.variant(RC_EN_SEL_A::RC_IN0)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in1(self) -> &'a mut W {
        self.variant(RC_EN_SEL_A::RC_IN1)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in2(self) -> &'a mut W {
        self.variant(RC_EN_SEL_A::RC_IN2)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn rc_in3(self) -> &'a mut W {
        self.variant(RC_EN_SEL_A::RC_IN3)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
        self.w
    }
}
#[doc = "Selects the operating mode for the clock to the associated UDB component block.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum RC_EN_MODE_A {
    #[doc = "0: No description available"]
    OFF = 0,
    #[doc = "1: No description available"]
    ON = 1,
    #[doc = "2: No description available"]
    POSEDGE = 2,
    #[doc = "3: No description available"]
    LEVEL = 3,
}
impl From<RC_EN_MODE_A> for u8 {
    #[inline(always)]
    fn from(variant: RC_EN_MODE_A) -> Self {
        variant as _
    }
}
#[doc = "Field `RC_EN_MODE` reader - Selects the operating mode for the clock to the associated UDB component block."]
pub struct RC_EN_MODE_R(crate::FieldReader<u8, RC_EN_MODE_A>);
impl RC_EN_MODE_R {
    pub(crate) fn new(bits: u8) -> Self {
        RC_EN_MODE_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RC_EN_MODE_A {
        match self.bits {
            0 => RC_EN_MODE_A::OFF,
            1 => RC_EN_MODE_A::ON,
            2 => RC_EN_MODE_A::POSEDGE,
            3 => RC_EN_MODE_A::LEVEL,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `OFF`"]
    #[inline(always)]
    pub fn is_off(&self) -> bool {
        **self == RC_EN_MODE_A::OFF
    }
    #[doc = "Checks if the value of the field is `ON`"]
    #[inline(always)]
    pub fn is_on(&self) -> bool {
        **self == RC_EN_MODE_A::ON
    }
    #[doc = "Checks if the value of the field is `POSEDGE`"]
    #[inline(always)]
    pub fn is_posedge(&self) -> bool {
        **self == RC_EN_MODE_A::POSEDGE
    }
    #[doc = "Checks if the value of the field is `LEVEL`"]
    #[inline(always)]
    pub fn is_level(&self) -> bool {
        **self == RC_EN_MODE_A::LEVEL
    }
}
impl core::ops::Deref for RC_EN_MODE_R {
    type Target = crate::FieldReader<u8, RC_EN_MODE_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_EN_MODE` writer - Selects the operating mode for the clock to the associated UDB component block."]
pub struct RC_EN_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_EN_MODE_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RC_EN_MODE_A) -> &'a mut W {
        self.bits(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn off(self) -> &'a mut W {
        self.variant(RC_EN_MODE_A::OFF)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn on(self) -> &'a mut W {
        self.variant(RC_EN_MODE_A::ON)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn posedge(self) -> &'a mut W {
        self.variant(RC_EN_MODE_A::POSEDGE)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn level(self) -> &'a mut W {
        self.variant(RC_EN_MODE_A::LEVEL)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2);
        self.w
    }
}
#[doc = "Optionally inverts the clock enable selection for the associated UDB component blocks.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RC_EN_INV_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<RC_EN_INV_A> for bool {
    #[inline(always)]
    fn from(variant: RC_EN_INV_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `RC_EN_INV` reader - Optionally inverts the clock enable selection for the associated UDB component blocks."]
pub struct RC_EN_INV_R(crate::FieldReader<bool, RC_EN_INV_A>);
impl RC_EN_INV_R {
    pub(crate) fn new(bits: bool) -> Self {
        RC_EN_INV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RC_EN_INV_A {
        match self.bits {
            false => RC_EN_INV_A::NOINV,
            true => RC_EN_INV_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == RC_EN_INV_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == RC_EN_INV_A::INVERT
    }
}
impl core::ops::Deref for RC_EN_INV_R {
    type Target = crate::FieldReader<bool, RC_EN_INV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_EN_INV` writer - Optionally inverts the clock enable selection for the associated UDB component blocks."]
pub struct RC_EN_INV_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_EN_INV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RC_EN_INV_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(RC_EN_INV_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(RC_EN_INV_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4);
        self.w
    }
}
#[doc = "Optionally inverts the clock selection for the associated UDB component block.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RC_INV_A {
    #[doc = "0: No description available"]
    NOINV = 0,
    #[doc = "1: No description available"]
    INVERT = 1,
}
impl From<RC_INV_A> for bool {
    #[inline(always)]
    fn from(variant: RC_INV_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `RC_INV` reader - Optionally inverts the clock selection for the associated UDB component block."]
pub struct RC_INV_R(crate::FieldReader<bool, RC_INV_A>);
impl RC_INV_R {
    pub(crate) fn new(bits: bool) -> Self {
        RC_INV_R(crate::FieldReader::new(bits))
    }
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> RC_INV_A {
        match self.bits {
            false => RC_INV_A::NOINV,
            true => RC_INV_A::INVERT,
        }
    }
    #[doc = "Checks if the value of the field is `NOINV`"]
    #[inline(always)]
    pub fn is_noinv(&self) -> bool {
        **self == RC_INV_A::NOINV
    }
    #[doc = "Checks if the value of the field is `INVERT`"]
    #[inline(always)]
    pub fn is_invert(&self) -> bool {
        **self == RC_INV_A::INVERT
    }
}
impl core::ops::Deref for RC_INV_R {
    type Target = crate::FieldReader<bool, RC_INV_A>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_INV` writer - Optionally inverts the clock selection for the associated UDB component block."]
pub struct RC_INV_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_INV_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RC_INV_A) -> &'a mut W {
        self.bit(variant.into())
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn noinv(self) -> &'a mut W {
        self.variant(RC_INV_A::NOINV)
    }
    #[doc = "No description available"]
    #[inline(always)]
    pub fn invert(self) -> &'a mut W {
        self.variant(RC_INV_A::INVERT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5);
        self.w
    }
}
#[doc = "Field `RC_RES_SEL0_OR_FRES` reader - Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is a firmware reset.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
pub struct RC_RES_SEL0_OR_FRES_R(crate::FieldReader<bool, bool>);
impl RC_RES_SEL0_OR_FRES_R {
    pub(crate) fn new(bits: bool) -> Self {
        RC_RES_SEL0_OR_FRES_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for RC_RES_SEL0_OR_FRES_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_RES_SEL0_OR_FRES` writer - Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is a firmware reset.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
pub struct RC_RES_SEL0_OR_FRES_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_RES_SEL0_OR_FRES_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
        self.w
    }
}
#[doc = "Field `RC_RES_SEL1` reader - Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is not used.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
pub struct RC_RES_SEL1_R(crate::FieldReader<bool, bool>);
impl RC_RES_SEL1_R {
    pub(crate) fn new(bits: bool) -> Self {
        RC_RES_SEL1_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for RC_RES_SEL1_R {
    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `RC_RES_SEL1` writer - Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is not used.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
pub struct RC_RES_SEL1_W<'a> {
    w: &'a mut W,
}
impl<'a> RC_RES_SEL1_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:1 - Selects channel route for enable control to the associated UDB component block"]
    #[inline(always)]
    pub fn rc_en_sel(&self) -> RC_EN_SEL_R {
        RC_EN_SEL_R::new((self.bits & 0x03) as u8)
    }
    #[doc = "Bits 2:3 - Selects the operating mode for the clock to the associated UDB component block."]
    #[inline(always)]
    pub fn rc_en_mode(&self) -> RC_EN_MODE_R {
        RC_EN_MODE_R::new(((self.bits >> 2) & 0x03) as u8)
    }
    #[doc = "Bit 4 - Optionally inverts the clock enable selection for the associated UDB component blocks."]
    #[inline(always)]
    pub fn rc_en_inv(&self) -> RC_EN_INV_R {
        RC_EN_INV_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 5 - Optionally inverts the clock selection for the associated UDB component block."]
    #[inline(always)]
    pub fn rc_inv(&self) -> RC_INV_R {
        RC_INV_R::new(((self.bits >> 5) & 0x01) != 0)
    }
    #[doc = "Bit 6 - Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is a firmware reset.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
    #[inline(always)]
    pub fn rc_res_sel0_or_fres(&self) -> RC_RES_SEL0_OR_FRES_R {
        RC_RES_SEL0_OR_FRES_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is not used.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
    #[inline(always)]
    pub fn rc_res_sel1(&self) -> RC_RES_SEL1_R {
        RC_RES_SEL1_R::new(((self.bits >> 7) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1 - Selects channel route for enable control to the associated UDB component block"]
    #[inline(always)]
    pub fn rc_en_sel(&mut self) -> RC_EN_SEL_W {
        RC_EN_SEL_W { w: self }
    }
    #[doc = "Bits 2:3 - Selects the operating mode for the clock to the associated UDB component block."]
    #[inline(always)]
    pub fn rc_en_mode(&mut self) -> RC_EN_MODE_W {
        RC_EN_MODE_W { w: self }
    }
    #[doc = "Bit 4 - Optionally inverts the clock enable selection for the associated UDB component blocks."]
    #[inline(always)]
    pub fn rc_en_inv(&mut self) -> RC_EN_INV_W {
        RC_EN_INV_W { w: self }
    }
    #[doc = "Bit 5 - Optionally inverts the clock selection for the associated UDB component block."]
    #[inline(always)]
    pub fn rc_inv(&mut self) -> RC_INV_W {
        RC_INV_W { w: self }
    }
    #[doc = "Bit 6 - Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is a firmware reset.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
    #[inline(always)]
    pub fn rc_res_sel0_or_fres(&mut self) -> RC_RES_SEL0_OR_FRES_W {
        RC_RES_SEL0_OR_FRES_W { w: self }
    }
    #[doc = "Bit 7 - Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (CFG31).?When ALT RES = '0' - This bit is not used.?When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following:?00 : rc_in \\[0\\]?01 : rc_in \\[1\\]?10 : rc_in \\[2\\]?11 : rc_in \\[3\\]"]
    #[inline(always)]
    pub fn rc_res_sel1(&mut self) -> RC_RES_SEL1_W {
        RC_RES_SEL1_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Datapath Clock and Reset control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg26](index.html) module"]
pub struct CFG26_SPEC;
impl crate::RegisterSpec for CFG26_SPEC {
    type Ux = u8;
}
#[doc = "`read()` method returns [cfg26::R](R) reader structure"]
impl crate::Readable for CFG26_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg26::W](W) writer structure"]
impl crate::Writable for CFG26_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets CFG26 to value 0"]
impl crate::Resettable for CFG26_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
